-
公开(公告)号：US09455725B2
公开(公告)日：2016-09-27
申请号：US14860711
申请日：2015-09-22
CPC分类号： H03L7/081 , H03K5/01 , H03K2005/00286 , H03L7/0807 , H03L7/091 , H03L7/095 , H03L7/1075 , H03L7/113
摘要： A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.
摘要翻译： 相位检测器包括多个采样电路，逻辑电路，多个解复用器和判定电路，其中多个采样电路使用具有不同相位的多个时钟信号来分别采样数据信号以产生多个采样 结果; 所述逻辑电路根据所述多个采样结果产生N个相位超前信号和N个相位滞后信号; 多个解复用器分别对N个相位超前信号和N个相位延迟信号执行解复用操作，分别产生M相前导输出信号和M相位滞后输出信号; 并且判决电路根据M相前导输出信号和M相位滞后输出信号产生最终相位超前信号和最终相位滞后信号。
-
公开(公告)号：US11569822B2
公开(公告)日：2023-01-31
申请号：US17355178
申请日：2021-06-23
发明人： Guo-Hau Lee , Huai-Te Wang , Cheng-Liang Hung
摘要： A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
-
公开(公告)号：US11411574B2
公开(公告)日：2022-08-09
申请号：US17215428
申请日：2021-03-29
摘要： A clock and data recovery circuit includes a phase detector (PD), a phase frequency detector (PFD), a multiplexer circuit, a conversion stage and an oscillator. The PD detects a difference in phase between a data signal and an oscillating signal to generate a first set of error signals. The PFD detects a difference in phase and frequency between a reference clock signal and the oscillating signal to generate a second set of error signals. The multiplexer circuit selectively outputs the first set of error signals or the second set of error signals as a third set of error signals according to a selection signal. The conversion stage determines a set of gains according to the selection signal, and converts the third set of error signals with the set of gains to generate a set of input signals. The oscillator generates the oscillating signal according to the set of input signals.
-
公开(公告)号：US20160142061A1
公开(公告)日：2016-05-19
申请号：US14860711
申请日：2015-09-22
CPC分类号： H03L7/081 , H03K5/01 , H03K2005/00286 , H03L7/0807 , H03L7/091 , H03L7/095 , H03L7/1075 , H03L7/113
摘要： A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.
摘要翻译： 相位检测器包括多个采样电路，逻辑电路，多个解复用器和判定电路，其中多个采样电路使用具有不同相位的多个时钟信号来分别采样数据信号以产生多个采样 结果; 所述逻辑电路根据所述多个采样结果产生N个相位超前信号和N个相位滞后信号; 多个解复用器分别对N个相位超前信号和N个相位延迟信号执行解复用操作，分别产生M相前导输出信号和M相位滞后输出信号; 并且判决电路根据M相前导输出信号和M相位滞后输出信号产生最终相位超前信号和最终相位滞后信号。
-
-
-
搜索结果
4 条记录 (耗时 0.014 秒)
