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公开(公告)号：US10714197B1
公开(公告)日：2020-07-14
申请号：US16388300
申请日：2019-04-18
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: A memory device and a program verification method thereof are provided. The write verification method includes: reading a previous page to obtain first read data, writing input data to a current page, reading the previous page or the current page to obtain second read data, and analyzing at least one of the first read data and the second read data to determine whether to back up at least one of the first read data and the input data to a redundant block of the memory device.
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2.发明授权公开(公告)号：US10026490B2
公开(公告)日：2018-07-17
申请号：US15288785
申请日：2016-10-07
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/26
Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.
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公开(公告)号：US09779820B1
公开(公告)日：2017-10-03
申请号：US15440889
申请日：2017-02-23
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/32 , G11C16/3427
Abstract: A non-volatile memory and a programming method thereof are provided. The programming method for the non-volatile memory includes: setting at least one first isolation cell between a first side cell and at least one first pass cell of an inhibited memory string; cutting off the at least one first isolation cell and providing a pre-boosting voltage to a word line of the first side cell and at a first time point; turning on the at least one first isolation cell at a second time point for transporting the pre-boosting potential to channels of the at least one first pass cell and a primary cell at a second time period; and providing a boosting voltage to word lines of the at least one first pass cell during a boosting time period.
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公开(公告)号：US09036393B2
公开(公告)日：2015-05-19
申请号：US14063284
申请日：2013-10-25
Applicant: MACRONIX International Co., Ltd.
Inventor： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
IPC: G11C17/06 , G11C17/16 , H01L21/822 , H01L27/10 , H01L27/06
CPC classification number: G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
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公开(公告)号：US20250124991A1
公开(公告)日：2025-04-17
申请号：US18488045
申请日：2023-10-17
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: A memory device and a programming method thereof are provided. The memory device has multiple word lines and a dummy word line set. A word line is selected from the word lines and is applied with a program voltage, and unselected word lines and the dummy word line set are applied with a pass voltage. After programming the selected word line, a program verification is performed on the selected word line. When the selected word line passes the program verification, a high bound and/or low bound check for the threshold voltage distribution of at least one of the dummy word lines is performed. When at least one of the dummy word lines fails in the high bound and/or low bound check, the status of the selected word line is shown as fail or a flag is set thereto.
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Patent Agency Ranking
公开(公告)号：US20240412793A1
公开(公告)日：2024-12-12
申请号：US18329583
申请日：2023-06-06
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: A non-volatile memory and a programming method thereof are provided. The programming method includes: performing a reading operation on a plurality of first memory cells of an Nth word line, and determining whether an equivalent threshold voltage is greater than a preset threshold value to generate a determination result, where N is a positive integer greater than 0; and in response to performing a programming operation on a plurality of second memory cells of an N+1th word line, deciding whether to adjust at least one selected programming verification voltage of a plurality of programming verification voltages by an offset value according to the determination result.
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公开(公告)号：US20180061503A1
公开(公告)日：2018-03-01
申请号：US15288785
申请日：2016-10-07
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/26
Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.
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公开(公告)号：US11145373B1
公开(公告)日：2021-10-12
申请号：US16882071
申请日：2020-05-22
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: A method for programming a memory device and a memory system are provided, wherein the method for programming the memory device includes steps below. First, a program command is proposed. Second, a width of a pulse about to provide to strings of memory cells of the memory device is determined according to a temperature data of the memory device. Then, the pulse is provided to the strings of memory cells to start doing a program operation. The width of the pulse becomes narrower as a temperature of the memory device is raised.
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公开(公告)号：US11056205B1
公开(公告)日：2021-07-06
申请号：US16908626
申请日：2020-06-22
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: A memory device and a write method thereof are provided. A control circuit performs a first write operation and a first write verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, and when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.
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公开(公告)号：US10460808B2
公开(公告)日：2019-10-29
申请号：US15793045
申请日：2017-10-25
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.
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