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公开(公告)号：US10340281B2
公开(公告)日：2019-07-02
申请号：US15458066
申请日：2017-03-14
发明人： Yu-Wei Jiang , Jia-Rong Chiou
IPC分类号： H01L27/11548 , H01L21/768 , H01L27/11556 , H01L27/11582 , H01L27/11575
摘要： A three-dimensional (3D) semiconductor device is provided, comprising a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer; and multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer in each of the sub-stacks.
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公开(公告)号：US10685971B2
公开(公告)日：2020-06-16
申请号：US16159753
申请日：2018-10-15
发明人： Yu-Wei Jiang , Chieh-Fang Chen , Jia-Rong Chiou
IPC分类号： H01L21/76 , H01L21/822 , H01L21/8234 , H01L27/11521 , H01L27/11556 , H01L27/11568 , H01L27/11582 , G11C5/02 , G11C5/06 , G11C5/12 , G11C16/04
摘要： A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.
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3.发明申请公开(公告)号：US20180261622A1
公开(公告)日：2018-09-13
申请号：US15456700
申请日：2017-03-13
发明人： Yu-Wei Jiang , Min-Feng Hung , Jia-Rong Chiou
IPC分类号： H01L27/11582 , H01L27/11568
CPC分类号： H01L27/11582 , H01L27/11568
摘要： A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.
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公开(公告)号：US11056504B2
公开(公告)日：2021-07-06
申请号：US16661040
申请日：2019-10-23
发明人： Yu-Wei Jiang , Jia-Rong Chiou
IPC分类号： H01L27/11582 , H01L27/11565 , H01L29/45 , H01L29/417 , H01L29/423 , H01L21/28 , H01L21/02 , H01L21/311 , H01L21/306
摘要： A memory device includes a channel element, a memory element, and an electrode element. The channel element has an open ring shape. A memory cell is defined in the memory element between the channel element and the electrode element.
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公开(公告)号：US20190067315A1
公开(公告)日：2019-02-28
申请号：US15690337
申请日：2017-08-30
发明人： Yu-Wei Jiang , Jia-Rong Chiou
IPC分类号： H01L27/11582 , H01L21/311
摘要： A 3D memory device includes a substrate, a multi-layers stack and a dielectric material. The substrate has a concave portion extending along a first direction into the substrate from a surface thereof. The multi-layers stack includes a plurality of conductive layers and a plurality of insulating layers alternatively stacked along the first direction on a bottom of the concave portion. The multi-layers stack also has at least one recess passing through the conductive layers and the insulating layers along the first direction, wherein the recess has a cross-sectional bottom profile and a cross-sectional opening profile perpendicular to the first direction and the cross-sectional bottom profile has a size substantially greater than that of the cross-sectional opening profile. The dielectric material is at least partially filled in the recess.
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公开(公告)号：US20180269214A1
公开(公告)日：2018-09-20
申请号：US15458066
申请日：2017-03-14
发明人： Yu-Wei Jiang , Jia-Rong Chiou
IPC分类号： H01L27/115 , H01L21/768
CPC分类号： H01L27/11548 , H01L21/76805 , H01L21/76816 , H01L21/76889 , H01L27/11556 , H01L27/11575 , H01L27/11582
摘要： A three-dimensional (3D) semiconductor device is provided, comprising a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer; and multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer in each of the sub-stacks.
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公开(公告)号：US20180261620A1
公开(公告)日：2018-09-13
申请号：US15454103
申请日：2017-03-09
发明人： Guan-Ru Lee , Jia-Rong Chiou
IPC分类号： H01L27/11582 , H01L27/11568
摘要： A 3D memory device includes a multi-layer stack, a first contact layer, a memory layer, a cannel layer. The multi-layer stack includes a plurality of conductive layers, a first opening and a second opening. The conductive layers are vertical stacked and insulated with each other. The first opening and the second opening respectively penetrate through at least two adjacent ones of the conductive layers. The first contact layer is disposed in the first opening and electrically connecting the conductive layers penetrated by the first opening. The memory layer is disposed in the second opening. The channel layer covers on the memory layer, wherein a plurality of memory cells are formed at cross points of the channel layer, the memory layer and the conductive layers penetrated by the second opening.
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公开(公告)号：US10475808B2
公开(公告)日：2019-11-12
申请号：US15690337
申请日：2017-08-30
发明人： Yu-Wei Jiang , Jia-Rong Chiou
IPC分类号： H01L51/05 , H01L29/66 , H01L21/02 , H01L29/10 , H01L29/775 , H01L29/78 , H01L27/11582 , H01L21/311
摘要： A 3D memory device includes a substrate, a multi-layers stack and a dielectric material. The substrate has a concave portion extending along a first direction into the substrate from a surface thereof. The multi-layers stack includes a plurality of conductive layers and a plurality of insulating layers alternatively stacked along the first direction on a bottom of the concave portion. The multi-layers stack also has at least one recess passing through the conductive layers and the insulating layers along the first direction, wherein the recess has a cross-sectional bottom profile and a cross-sectional opening profile perpendicular to the first direction and the cross-sectional bottom profile has a size substantially greater than that of the cross-sectional opening profile. The dielectric material is at least partially filled in the recess.
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公开(公告)号：US10002879B2
公开(公告)日：2018-06-19
申请号：US15092856
申请日：2016-04-07
发明人： Yu-Wei Jiang , Jia-Rong Chiou
IPC分类号： H01L27/11582 , H01L27/11568 , H01L23/522 , H01L23/532 , H01L29/10 , H01L29/04 , H01L29/16
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/53257 , H01L27/11568 , H01L28/00 , H01L29/04 , H01L29/1037 , H01L29/16
摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate. Each of the first stacked structures includes alternately stacked metal layers and oxide layers. Each of the second stacked structures includes alternately stacked silicon nitride layers and oxide layers. The first stacked structures are disposed between the two second stacked structures.
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公开(公告)号：US20170294444A1
公开(公告)日：2017-10-12
申请号：US15092856
申请日：2016-04-07
发明人： Yu-Wei Jiang , Jia-Rong Chiou
IPC分类号： H01L27/115 , H01L29/16 , H01L29/10 , H01L29/04 , H01L23/522 , H01L23/532
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/53257 , H01L27/11568 , H01L28/00 , H01L29/04 , H01L29/1037 , H01L29/16
摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate. Each of the first stacked structures includes alternately stacked metal layers and oxide layers. Each of the second stacked structures includes alternately stacked silicon nitride layers and oxide layers. The first stacked structures are disposed between the two second stacked structures.
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