公开(公告)号：US20230009065A1

公开(公告)日：2023-01-12

申请号：US17368700

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4096 ,  G11C5/06

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20230317143A1

公开(公告)日：2023-10-05

申请号：US18206422

申请日：2023-06-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/102 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20230007890A1

公开(公告)日：2023-01-12

申请号：US17368705

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C16/10 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20220215862A1

公开(公告)日：2022-07-07

申请号：US17701044

申请日：2022-03-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long CHANG ,  Su-Chueh LO ,  Yung-Feng LIN

IPC: G11C7/10 ,  G11C7/22 ,  G06F9/445 ,  G06F9/38

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.

公开(公告)号：US20210280222A1

公开(公告)日：2021-09-09

申请号：US17070340

申请日：2020-10-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long CHANG ,  Su-Chueh LO ,  Yung-Feng LIN

IPC: G11C7/10 ,  G11C7/22 ,  G06F9/38 ,  G06F9/445

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

公开(公告)号：US20220375523A1

公开(公告)日：2022-11-24

申请号：US17325243

申请日：2021-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng LIN ,  Su-Chueh LO ,  Teng-Hao YEH ,  Hang-Ting LUE

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.