公开(公告)号：US20240231623A9

公开(公告)日：2024-07-11

申请号：US18049303

申请日：2022-10-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chih CHIEN ,  Cheng-Lin SUNG ,  Hsiang-Lan LUNG

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

公开(公告)号：US20230130293A1

公开(公告)日：2023-04-27

申请号：US17574629

申请日：2022-01-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chih CHIEN ,  Hsiang-Lan LUNG

IPC: G11C29/12 ,  G11C11/402

Abstract: A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.

公开(公告)号：US20220407000A1

公开(公告)日：2022-12-22

申请号：US17349359

申请日：2021-06-16

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chih-Hsiang YANG ,  Hsiang-Lan LUNG ,  Wei-Chih CHIEN ,  Cheng-Wei CHENG ,  Matthew J. BRIGHTSKY

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell formed in a pillar structure between a first electrode and a second electrode includes laminated encapsulation structure. In one example, the pillar includes a body of ovonic threshold switch material, carbon-based intermediate layers, metal layers and a body of phase change memory material in electrical series between the first and second electrodes. The laminated encapsulation structure surrounds the pillar. The laminated dielectric encapsulation structure comprises at least three conformal layers, including a first layer of material, a second conformal layer of a second layer material different from the first layer material; and a third conformal layer of a third layer material different from the second layer material.

公开(公告)号：US20250089268A1

公开(公告)日：2025-03-13

申请号：US18464326

申请日：2023-09-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG ,  Wei-Chih CHIEN

IPC: H10B63/00 ,  H10N70/00

Abstract: A semiconductor device includes a stack including a plurality of insulating layers and a plurality of word plane conductors alternately arranged, a vertical pillar structure disposed in the stack, and a plurality of outer electrodes. The vertical pillar structure includes a conductive core, an inner electrode on a sidewall of the conductive core, and an ovonic threshold switch (OTS) layer on a sidewall of the inner electrode, in which the inner electrode is disposed between the conductive core and the OTS layer. The outer electrodes are disposed between the OTS layer and the word plane conductors, wherein a resistance of a material of the word plane conductors is less than a resistance of a material of the outer electrodes. A method of forming the semiconductor device is also disclosed.

公开(公告)号：US20210249600A1

公开(公告)日：2021-08-12

申请号：US16787371

申请日：2020-02-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chih CHIEN ,  Hsiang-Lan LUNG

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory element comprises a carbon deposit, such as a carbon buffer layer, on a body of phase change memory material, disposed between first and second electrodes. A carbon deposit is found to improve endurance of phase change memory cells by five orders of magnitude or more. Examples include “mushroom” style memory elements, as well as other types including 3D arrays of cross-point elements.

公开(公告)号：US20130028005A1

公开(公告)日：2013-01-31

申请号：US13624761

申请日：2012-09-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chih CHIEN ,  Ming-Hsiu LEE ,  Feng-Ming LEE

IPC: G11C11/21 ,  H01L45/00

CPC classification number: G11C13/004 ,  G11C11/5614 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2213/51 ,  G11C2213/71 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146

Abstract: A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance. A resistive memory array including an array of the above resistive memory units, word lines and bit lines is also described, wherein the word (bit) lines are coupled to the first (second) memory layers.

Abstract translation: 提供了一种用于控制电阻性存储器的操作的电阻性存储器和方法。 电阻性存储器具有第一存储器层，第二存储器层和介质层。 第一存储器层和第二存储器层中的每一个用于存储数据。 介质层形成在第一存储层和第二存储层之间。 该方法至少包括测量第一存储层和第二存储层之间的电阻的步骤，以及根据测得的电阻确定第一状态，第二状态和第三状态中的哪一种是电阻性存储器的状态 。 还描述了包括上述电阻性存储器单元，字线和位线的阵列的电阻式存储器阵列，其中字（位）线耦合到第一（第二）存储器层。

公开(公告)号：US20240134529A1

公开(公告)日：2024-04-25

申请号：US18049303

申请日：2022-10-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chih CHIEN ,  Cheng-Lin SUNG ,  Hsiang-Lan LUNG

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

公开(公告)号：US20150214479A1

公开(公告)日：2015-07-30

申请号：US14603647

申请日：2015-01-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsiang-Lan LUNG ,  Chao-I WU ,  Wei-Chih CHIEN

IPC: H01L45/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  H01L45/06 ,  H01L45/144

Abstract: A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.

Abstract translation: 一种装置包括具有存储元件的第一和第二多个存储单元，以及在第一和第二多个存储单元上的第一和第二封盖材料。 第一和第二封盖材料可以包括较低和较高密度的氮化硅。 存储器元件可以包括可编程电阻存储器材料，并且封盖材料可以接触存储器元件。 第一和第二多个存储器单元可以具有公共的单元结构。 罐中的第一存储器单元可以包括顶部和底部电极，其间具有记忆材料，并且第一封盖材料与记忆材料接触。 控制电路可以对第一和第二多个存储单元应用不同的写入算法。 通过使用不同的封盖材料但是具有相同的单元结构形成第一和第二封盖层，第一和第二组存储器单元可以具有不同的操作存储器特性。