公开(公告)号：US20180366573A1

公开(公告)日：2018-12-20

申请号：US15624490

申请日：2017-06-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Fu-Hsing Chou ,  Yao-Fu Chan ,  Tzung-Ting Han

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device, a memory device, and a manufacturing method of the same are provided. The memory device includes a substrate, a floating gate, a gate insulation layer, an inter-gate dielectric layer, and a control gate. The control gate is a multi-layer structure with three or more layers, and at least one layer of the multi-layer structure is a metal silicide layer.

公开(公告)号：US10056395B2

公开(公告)日：2018-08-21

申请号：US15290470

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chi-Pin Lu ,  Pei-Ci Jhang ,  Fu-Hsing Chou ,  Chih-Hsiung Lee

IPC: H01L29/00 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/04 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027 ,  H01L21/306 ,  H01L21/768 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76802 ,  H01L27/11526 ,  H01L28/00 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/36

Abstract: A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.