公开(公告)号：US10714494B2

公开(公告)日：2020-07-14

申请号：US15821832

申请日：2017-11-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Pei-Ci Jhang ,  Chi-Pin Lu

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1157

Abstract: Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.

公开(公告)号：US20140209990A1

公开(公告)日：2014-07-31

申请号：US13749828

申请日：2013-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chi-Pin Lu

IPC: H01L29/792 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device is provided having an improved gate coupling ratio, substantial suppression of p-type dopant segregation, and reduction in inter-poly dielectric current leakage. The memory device may be substantially free of any void spaces in a second conductive layer. Methods of manufacturing such a memory device are also provided.

Abstract translation: 提供了一种存储器件，其具有改进的栅极耦合比，对p型掺杂剂偏析的实质性抑制以及多晶硅间介质电流泄漏的减少。 存储器件可以在第二导电层中基本上没有任何空隙。 还提供了制造这种存储器件的方法。

公开(公告)号：US20190157290A1

公开(公告)日：2019-05-23

申请号：US15821832

申请日：2017-11-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Pei-Ci Jhang ,  Chi-Pin Lu

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/28

Abstract: Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.

公开(公告)号：US11895841B2

公开(公告)日：2024-02-06

申请号：US17485636

申请日：2021-09-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Pei-Ci Jhang ,  Chi-Pin Lu

IPC: H01L27/11568 ,  H10B43/30 ,  H10B43/20

CPC classification number: H10B43/30 ,  H10B43/20

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

公开(公告)号：US10181475B2

公开(公告)日：2019-01-15

申请号：US15294338

申请日：2016-10-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Pei-Ci Jhang ,  Chi-Pin Lu ,  Jung-Yu Shieh

IPC: H01L21/00 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/1157

Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.

公开(公告)号：US10056395B2

公开(公告)日：2018-08-21

申请号：US15290470

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chi-Pin Lu ,  Pei-Ci Jhang ,  Fu-Hsing Chou ,  Chih-Hsiung Lee

IPC: H01L29/00 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/04 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027 ,  H01L21/306 ,  H01L21/768 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76802 ,  H01L27/11526 ,  H01L28/00 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/36

Abstract: A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.

公开(公告)号：US20180019254A1

公开(公告)日：2018-01-18

申请号：US15294338

申请日：2016-10-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Pei-Ci Jhang ,  Chi-Pin Lu ,  Jung-Yu Shieh

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.