公开(公告)号：US20140264726A1

公开(公告)日：2014-09-18

申请号：US13920565

申请日：2013-06-18

Applicant: Macronix International Co., Ltd.

Inventor： Yao-Fu Chan ,  Ta-Kang Chu ,  Pi-Shan Tseng

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229

Abstract: A semiconductor device is provided having reduced corner thinning in a shallow trench isolation (STI) structure of the periphery region. The semiconductor device may be substantially free of any corner thinning at a corner of a STI structure of the periphery region. Methods of manufacturing such a semiconductor device are also provided.

Abstract translation: 提供了一种半导体器件，其具有在外围区域的浅沟槽隔离（STI）结构中具有减小的角部变薄。 半导体器件可以在外围区域的STI结构的拐角处基本上没有任何角部变薄。 还提供了制造这种半导体器件的方法。

公开(公告)号：US09620518B2

公开(公告)日：2017-04-11

申请号：US14681980

申请日：2015-04-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-Fu Chan

IPC: H01L21/336 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/792 ,  H01L29/10

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/1037 ,  H01L29/7926

Abstract: A method of fabricating a semiconductor device is provided. A stack layer is formed on a substrate. The stack layer is patterned to form a plurality of stack structures extending in a first direction. A trench extending in the first direction is located between two adjacent stack structures. Each trench has a plurality of wide portions and a plurality of narrow portions. A maximum width of the wide portions in a second direction is larger than a maximum width of the narrow portions in the second direction. A charge storage layer is formed to cover a bottom surface and sidewalls of the wide portion and fill up the narrow portion. A conductive layer is formed to fill up the wide portion. A semiconductor device formed by the method is also provided.

公开(公告)号：US20160300849A1

公开(公告)日：2016-10-13

申请号：US14681980

申请日：2015-04-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-Fu Chan

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/10 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/1037 ,  H01L29/7926

Abstract: A method of fabricating a semiconductor device is provided. A stack layer is formed on a substrate. The stack layer is patterned to form a plurality of stack structures extending in a first direction. A trench extending in the first direction is located between two adjacent stack structures. Each trench has a plurality of wide portions and a plurality of narrow portions. A maximum width of the wide portions in a second direction is larger than a maximum width of the narrow portions in the second direction. A charge storage layer is formed to cover a bottom surface and sidewalls of the wide portion and fill up the narrow portion. A conductive layer is formed to fill up the wide portion. A semiconductor device formed by the method is also provided.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成堆叠层。 图案化堆叠层以形成沿第一方向延伸的多个堆叠结构。 沿第一方向延伸的沟槽位于两个相邻的堆叠结构之间。 每个沟槽具有多个宽部分和多个窄部分。 第二方向上的宽部的最大宽度大于第二方向上的窄部的最大宽度。 形成电荷存储层以覆盖宽部分的底表面和侧壁并填满窄部分。 形成导电层以填充宽部分。 还提供了通过该方法形成的半导体器件。

公开(公告)号：US09431406B1

公开(公告)日：2016-08-30

申请号：US14724573

申请日：2015-05-28

Applicant: MACRONIX International Co., Ltd.

Inventor： Ting-Feng Liao ,  Yao-Fu Chan

IPC: H01L27/115 ,  H01L21/265 ,  H01L21/266 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66825

Abstract: A semiconductor device and a method of forming the same are provided. At least two separated stacked structures and at least two hard mask patterns respectively on the stacked structures are formed on a substrate. A patterned mask layer is formed on the substrate. The patterned mask layer has an opening which exposes a portion of top surfaces of the hard mask patterns and a portion of the substrate between the stacked structures. The exposed portion of the substrate is removed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a trench in the substrate. An ion implantation process is performed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a doped region in the substrate around the trench.

Abstract translation: 提供半导体器件及其形成方法。 在基板上形成分别在堆叠结构上的至少两个分离的堆叠结构和至少两个硬掩模图案。 在基板上形成图案化的掩模层。 图案化掩模层具有暴露硬掩模图案的顶表面的一部分和在堆叠结构之间的衬底的一部分的开口。 通过使用图案化掩模层和硬掩模图案作为掩模来去除衬底的暴露部分，以便在衬底中形成沟槽。 通过使用图案化掩模层和硬掩模图案作为掩模来执行离子注入工艺，以在沟槽周围的衬底中形成掺杂区域。

公开(公告)号：US20180366573A1

公开(公告)日：2018-12-20

申请号：US15624490

申请日：2017-06-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Fu-Hsing Chou ,  Yao-Fu Chan ,  Tzung-Ting Han

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device, a memory device, and a manufacturing method of the same are provided. The memory device includes a substrate, a floating gate, a gate insulation layer, an inter-gate dielectric layer, and a control gate. The control gate is a multi-layer structure with three or more layers, and at least one layer of the multi-layer structure is a metal silicide layer.

公开(公告)号：US09196567B1

公开(公告)日：2015-11-24

申请号：US14597099

申请日：2015-01-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-Fu Chan

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L21/8229

CPC classification number: H01L24/06 ,  H01L21/8229 ,  H01L23/48 ,  H01L23/5221 ,  H01L23/528 ,  H01L24/05 ,  H01L27/11548 ,  H01L27/11575 ,  H01L2224/0345 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/06102 ,  H01L2924/00014

Abstract: A pad structure including a plurality of staircase structures is provided. The staircase structures are disposed on the substrate. Each of the staircase structures includes a plurality of conductor layers and a plurality of dielectric layers that are alternately stacked. Two adjacent staircase structures are connected with each other by sharing the conductor layers and the dielectric layers and are arranged in parallel along a first direction. One of the two adjacent staircase structures includes at least one staircase portion that gradually decreases in height along a second direction, and the other of the two adjacent staircase structures includes at least one staircase portion that gradually decreases in height along a direction opposite to the second direction.

Abstract translation: 提供了包括多个阶梯结构的焊盘结构。 楼梯结构设置在基板上。 每个楼梯结构包括交替层叠的多个导体层和多个电介质层。 两个相邻的楼梯结构通过共享导体层和电介质层并沿第一方向平行布置而相互连接。 两个相邻的楼梯结构中的一个包括至少一个沿第二方向逐渐降低高度的阶梯部分，并且两个相邻阶梯结构中的另一个包括至少一个阶梯部分，该阶梯部分沿着与第二方向相反的方向逐渐降低高度 方向。