中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.014 seconds)

    MANAGING POWER SUPPLY IN SEMICONDUCTOR DEVICES
    1.
    发明申请
    MANAGING POWER SUPPLY IN SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250095751A1

    公开(公告)日：2025-03-20

    申请号：US18467047

    申请日：2023-09-14

    Applicant: Macronix International Co., Ltd.

    Inventor： Shin-Jang Shen ,  Chun-Lien Su ,  Shih-Chou Juan

    IPC: G11C16/30

    Abstract: Systems, devices, methods, and circuits for managing power supply in semiconductor devices are provided. The semiconductor devices can include 3D NAND flash memory devices with high capacity and/or high performance. In one aspect, a semiconductor device includes: a voltage pump, a pump switch circuit configured to be coupled to the voltage pump, and an interface including a voltage pin coupled to the pump switch circuit. The voltage pump has an input, an output, and a series of pump stages coupled between the input and the output. The pump switch circuit is configured to provide an input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages of the series of pump stages to output a target voltage at the output of the voltage pump.

    Continuous read with multiple read commands
    2.
    发明授权
    Continuous read with multiple read commands 有权

    公开(公告)号：US11734181B2

    公开(公告)日：2023-08-22

    申请号：US17579428

    申请日：2022-01-19

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shuo-Nan Hung ,  Chun-Lien Su

    IPC: G06F12/08 ,  G06F12/0882

    CPC classification number: G06F12/0882 ,  G06F2212/1024 ,  G06F2212/2022

    Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.

    Managing status information of logic units
    3.
    发明授权
    Managing status information of logic units 有权

    公开(公告)号：US12112165B2

    公开(公告)日：2024-10-08

    申请号：US17956155

    申请日：2022-09-29

    Applicant: Macronix International Co., Ltd.

    Inventor： Sheng-Lun Wu ,  Chun-Lien Su

    IPC: G06F9/30 ,  G06F1/08 ,  G06F9/54

    CPC classification number: G06F9/30021 ,  G06F1/08 ,  G06F9/544

    Abstract: Systems, methods, and apparatus including computer-readable mediums for managing status information of logic units are provided. In one aspect, a device includes a semiconductor device including one or more logic units and a reporting bus and a controller coupled to the semiconductor device and configured to store status information of the one or more logic units in the semiconductor device. Each of the one or more logic units is configured to send information associated with the logic unit using a corresponding reporting unit in the semiconductor device through the reporting bus to the controller to indicate a status of the logic unit. The controller is configured to, in response to receiving the information associated with the logic unit, update corresponding status information of the logic unit based on the status of the logic unit.

    In-place refresh operation in flash memory
    6.
    发明授权
    In-place refresh operation in flash memory 有权

    公开(公告)号：US11087858B1

    公开(公告)日：2021-08-10

    申请号：US16938500

    申请日：2020-07-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shuo-Nan Hung ,  Chun-Lien Su

    IPC: G11C16/16 ,  G11C29/44 ,  G11C29/42 ,  G11C16/26 ,  G11C29/00 ,  G11C29/18

    Abstract: A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.

    MULTI-CIRCUIT CONTROL SYSTEM AND READING METHOD FOR STATUS INFORMATION THEREOF
    7.
    发明申请
    MULTI-CIRCUIT CONTROL SYSTEM AND READING METHOD FOR STATUS INFORMATION THEREOF 有权

    公开(公告)号：US20250087253A1

    公开(公告)日：2025-03-13

    申请号：US18464262

    申请日：2023-09-11

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Shuo-Nan Hung ,  Shih-Chou Juan ,  Chun-Lien Su

    IPC: G11C7/10

    Abstract: Disclosed are a multi-circuit control system and a reading method for status information thereof. The multi-circuit control system includes a first circuit and N second circuits. The second circuit is, for example a three dimensional NAND flash memory circuit, and the multi-circuit control system provides a storage media with high-performance and high-capacity. The first circuit provides a read clock signal. The second circuits are coupled in series, and coupled to the first circuit. Each of the second circuits has at least one first data shifter. The at least one data shifter is used to load status information of each of the second circuits, and shift out each of the status information to a second circuit of a previous stage or the first circuit or the first chip obtains the status information of each of the second circuits through a parallel transmission scheme.

    FLASH MEMORY AND WRITING METHOD THEREOF
    9.
    发明申请
    FLASH MEMORY AND WRITING METHOD THEREOF 有权

    公开(公告)号：US20220283738A1

    公开(公告)日：2022-09-08

    申请号：US17192807

    申请日：2021-03-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chun-Lien Su ,  Chang-Ting Chen

    IPC: G06F3/06 ,  G06F12/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

    Abstract: A flash memory and a writing method thereof are provided. The flash memory includes a plurality of memory blocks and a plurality of multiplex circuits. The memory blocks are arranged into a plurality of memory banks. Each of the memory blocks transmits a plurality of erase voltages or a plurality of program voltages to the corresponding memory bank for executing an erase operation or a program operation. The program operation is executed by one of the memory banks while the erase operation is executed by another one of the memory banks according to a programming while erasing instruction.

    Continuous read with multiple read commands
    10.
    发明授权
    Continuous read with multiple read commands 有权

    公开(公告)号：US11249913B2

    公开(公告)日：2022-02-15

    申请号：US17061451

    申请日：2020-10-01

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shuo-Nan Hung ,  Chun-Lien Su

    IPC: G06F12/08 ,  G06F12/0882

    Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.

Patent Agency Ranking