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公开(公告)号：US11340641B2
公开(公告)日：2022-05-24
申请号：US16590391
申请日：2019-10-02
Applicant: MEDIATEK INC.
Inventor： Chun-Wei Chang , Song-Yu Yang , Ang-Sheng Lin
Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.
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Patent Agency Ranking
公开(公告)号：US10291237B2
公开(公告)日：2019-05-14
申请号：US15355073
申请日：2016-11-18
Applicant: MEDIATEK INC.
Inventor： Hao-Wei Huang , Yen-Tso Chen , Song-Yu Yang
Abstract: An oscillator circuit has a reconfigurable oscillator amplifier. The reconfigurable oscillator amplifier is used to be coupled to a resonant circuit in parallel. The reconfigurable oscillator amplifier supports different circuit configurations for different operation modes, respectively. The reconfigurable oscillator amplifier has at least one circuit component shared by the different circuit configurations. The reconfigurable oscillator amplifier employs one of the different circuit configurations under one of the different operation modes.
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3.发明公开公开(公告)号：US20240171162A1
公开(公告)日：2024-05-23
申请号：US18234346
申请日：2023-08-15
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Song-Yu Yang , Ang-Sheng Lin
CPC classification number: H03K5/01 , H03L7/08 , H03K2005/00058
Abstract: A phase error compensation circuit and a method for compensating a phase error between a reference clock and a feedback clock are provided. The phase error compensation circuit includes a first programmable delay circuit, a second programmable delay circuit and at least one swapping circuit. The first programmable delay circuit provides a first delay. The second programmable delay circuit provides a second delay. At a present cycle, the first delay is unchanged, wherein the swapping circuit applies the first delay to the feedback clock for generating a compensated feedback clock and applies the second delay to the reference clock for generating a compensated reference clock. At a next cycle, the second delay is unchanged, where the swapping circuit applies the second delay to the feedback clock for generating the compensated feedback clock and applies the first delay to the reference clock for generating the compensated reference clock.
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公开(公告)号：US11837995B2
公开(公告)日：2023-12-05
申请号：US17730221
申请日：2022-04-27
Applicant: MEDIATEK INC.
Inventor： Hao-Wei Huang , Song-Yu Yang , Ang-Sheng Lin , Yi-Chien Tsai
CPC classification number: H03B5/08 , H01F27/2823 , H01F27/40 , H03B5/1265 , H03B5/1268 , H03B2200/009
Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.
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公开(公告)号：US20220385233A1
公开(公告)日：2022-12-01
申请号：US17730221
申请日：2022-04-27
Applicant: MEDIATEK INC.
Inventor： Hao-Wei Huang , Song-Yu Yang , Ang-Sheng Lin , Yi-Chien Tsai
Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.
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6.发明申请公开(公告)号：US20170294915A1
公开(公告)日：2017-10-12
申请号：US15355073
申请日：2016-11-18
Applicant: MEDIATEK INC.
Inventor： Hao-Wei Huang , Yen-Tso Chen , Song-Yu Yang
CPC classification number: H03L5/00 , H03B5/06 , H03B5/1262 , H03B5/24 , H03B5/364 , H03B2200/0082 , H03B2200/009 , H03B2200/0094 , H03B2201/0266 , H03L3/00
Abstract: An oscillator circuit has a reconfigurable oscillator amplifier. The reconfigurable oscillator amplifier is used to be coupled to a resonant circuit in parallel. The reconfigurable oscillator amplifier supports different circuit configurations for different operation modes, respectively. The reconfigurable oscillator amplifier has at least one circuit component shared by the different circuit configurations. The reconfigurable oscillator amplifier employs one of the different circuit configurations under one of the different operation modes.
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