公开(公告)号：US20190123062A1

公开(公告)日：2019-04-25

申请号：US16048418

申请日：2018-07-30

Applicant: MEDIATEK Inc.

Inventor： Chuan-Shian FU ,  Cheng-Jyi CHANG ,  Shao-Hwang SHER

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a substrate and a plurality of standard cells. The standard cells are formed on the substrate, wherein each standard cell comprises a first fin, a second fin and a third fin, the second fin is located between the first fin and the third fin, and there is a first interval between the first fin and the second fin is different from a second interval between the first fin and the third fin.

公开(公告)号：US20230125239A1

公开(公告)日：2023-04-27

申请号：US17934233

申请日：2022-09-22

Applicant: MEDIATEK INC.

Inventor： Hsiao-Yun CHEN ,  Yao-Tsung HUANG ,  Cheng-Jyi CHANG

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second through via, a molding material, a second semiconductor die, and a second redistribution layer. The first semiconductor die is disposed over the first redistribution layer and includes a first through via having a first width. The second through via is adjacent to the first semiconductor die and has a second width. The second width is greater than the first width. The molding material surrounds the first semiconductor die and the second through via. The second semiconductor die is disposed over the molding material and is electrically coupled to the first through via and the second through via. The second redistribution layer is disposed over the second semiconductor die.

公开(公告)号：US20230260977A1

公开(公告)日：2023-08-17

申请号：US17962185

申请日：2022-10-07

Applicant: MediaTek Inc.

Inventor： Hsiao-Yun CHEN ,  Chi-Hung HUANG ,  Yao-Tsung HUANG ,  Cheng-Jyi CHANG ,  Sheng Chieh CHANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L25/162 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/165 ,  H01L24/73 ,  H01L24/80 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L28/75 ,  H01L28/90 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/19041 ,  H01L2924/19011 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Various embodiments of a 3DIC die package, including trench capacitors integrated with IC dies, are disclosed. A 3DIC die package includes a first IC die and a second IC die disposed on the first IC die. The first IC die includes a substrate having a first surface and a second surface opposite to the first surface, a first active device disposed on the first surface of the substrate, and a passive device disposed on the second surface of the substrate. The passive device includes a plurality of trenches disposed in the substrate and through the second surface of the substrate, first and second conductive layers disposed in the plurality of trenches and on the second surface of the substrate, and a first dielectric layer disposed between the first and second conductive layers. The second IC die includes a second active device.

公开(公告)号：US20210320040A1

公开(公告)日：2021-10-14

申请号：US17218328

申请日：2021-03-31

Applicant: MEDIATEK INC.

Inventor： Chuan-Shian FU ,  Cheng-Jyi CHANG

IPC: H01L23/02 ,  H01L23/538 ,  H01L23/544

Abstract: A semiconductor structure includes a base layer, semiconductor dies on the base layer, and an inter-die connection layer electrically connecting two adjacent semiconductor dies. Each of the semiconductor dies includes an active area and a seal ring area including a seal ring surrounding the active area. The inter-die connection layer extends over adjacent portions of the seal rings in the seal ring areas of the two adjacent semiconductor dies.