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公开(公告)号：US20240186209A1
公开(公告)日：2024-06-06
申请号：US18499383
申请日：2023-11-01
申请人： MEDIATEK INC.
发明人： Tai-Hao PENG , Yao-Tsung HUANG
IPC分类号： H01L23/367 , H01L23/00 , H01L23/31 , H01L23/498
CPC分类号： H01L23/367 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L24/16 , H01L25/105 , H01L2224/16227
摘要： A semiconductor package structure includes a substrate, a semiconductor die, a molding material, an interposer, and a thermal via. The substrate has a wiring structure. The semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. The molding material surrounds the semiconductor die. The interposer is disposed over the semiconductor die. The thermal via is disposed in the interposer and extends to a bottom surface of the interposer. The thermal via vertically overlaps the semiconductor die.
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公开(公告)号：US20230260977A1
公开(公告)日：2023-08-17
申请号：US17962185
申请日：2022-10-07
申请人： MediaTek Inc.
IPC分类号： H01L25/16 , H01L23/00 , H01L23/48 , H01L23/498 , H01L49/02
CPC分类号： H01L25/162 , H01L24/08 , H01L24/16 , H01L24/32 , H01L25/165 , H01L24/73 , H01L24/80 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L28/75 , H01L28/90 , H01L2924/1434 , H01L2924/1431 , H01L2924/19041 , H01L2924/19011 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/08235 , H01L2224/08265 , H01L2224/80895 , H01L2224/80896
摘要： Various embodiments of a 3DIC die package, including trench capacitors integrated with IC dies, are disclosed. A 3DIC die package includes a first IC die and a second IC die disposed on the first IC die. The first IC die includes a substrate having a first surface and a second surface opposite to the first surface, a first active device disposed on the first surface of the substrate, and a passive device disposed on the second surface of the substrate. The passive device includes a plurality of trenches disposed in the substrate and through the second surface of the substrate, first and second conductive layers disposed in the plurality of trenches and on the second surface of the substrate, and a first dielectric layer disposed between the first and second conductive layers. The second IC die includes a second active device.
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公开(公告)号：US20190123176A1
公开(公告)日：2019-04-25
申请号：US16121730
申请日：2018-09-05
申请人： MEDIATEK Inc.
IPC分类号： H01L29/66 , H01L29/78 , H01L29/417 , H01L27/12 , H01L21/8238 , H01L21/84
摘要： A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
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公开(公告)号：US20230387025A1
公开(公告)日：2023-11-30
申请号：US18191092
申请日：2023-03-28
申请人： MEDIATEK Inc.
发明人： Tai-Hao PENG , Yao-Tsung HUANG
IPC分类号： H01L23/538 , H01L23/31 , H01L21/56
CPC分类号： H01L23/5381 , H01L23/5384 , H01L23/5386 , H01L23/3135 , H01L21/56
摘要： A semiconductor device includes a first layer structure, a second layer structure, a bridge die, a first SoC and a second SoC. The bridge die is disposed between the first layer structure and the second layer structure. The first SoC and the second SoC are disposed on the second layer structure. The first SoC and the second SoC are electrically connected through the bridge die.
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公开(公告)号：US20230125239A1
公开(公告)日：2023-04-27
申请号：US17934233
申请日：2022-09-22
申请人： MEDIATEK INC.
发明人： Hsiao-Yun CHEN , Yao-Tsung HUANG , Cheng-Jyi CHANG
IPC分类号： H01L25/18 , H01L23/48 , H01L23/31 , H01L23/00 , H01L23/498
摘要： A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second through via, a molding material, a second semiconductor die, and a second redistribution layer. The first semiconductor die is disposed over the first redistribution layer and includes a first through via having a first width. The second through via is adjacent to the first semiconductor die and has a second width. The second width is greater than the first width. The molding material surrounds the first semiconductor die and the second through via. The second semiconductor die is disposed over the molding material and is electrically coupled to the first through via and the second through via. The second redistribution layer is disposed over the second semiconductor die.
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公开(公告)号：US20220406921A1
公开(公告)日：2022-12-22
申请号：US17821195
申请日：2022-08-22
申请人： MEDIATEK Inc.
IPC分类号： H01L29/66 , H01L29/78 , H01L21/84 , H01L27/12 , H01L21/8238 , H01L29/417 , H01L27/088 , H01L21/8234
摘要： A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
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公开(公告)号：US20160197071A1
公开(公告)日：2016-07-07
申请号：US14861461
申请日：2015-09-22
申请人： MediaTek Inc.
发明人： Chao-Yang YEH , Yi-Feng CHEN , Jia-Wei FANG , Yao-Tsung HUANG , Ming-Cheng LEE
IPC分类号： H01L27/08 , H01L49/02 , H01L21/283
CPC分类号： H01L27/0805 , H01L23/485 , H01L23/5223 , H01L27/0207 , H01L28/86
摘要： The invention provides an integrated circuit device. The integrated circuit device includes a semiconductor substrate. An isolation structure is positioned in the semiconductor substrate. A first electrode and a second electrode are positioned on the semiconductor substrate and coupled to different voltage supplies. The first electrode laterally or parallelly overlaps the second electrode. The first electrode and the second electrode vertically overlap the isolation structure. As a result, leakage current is mitigated or eliminated so that the reliability and performance of the integrated circuit device are improved.
摘要翻译： 本发明提供一种集成电路装置。 集成电路器件包括半导体衬底。 隔离结构位于半导体衬底中。 第一电极和第二电极位于半导体衬底上并耦合到不同的电压源。 第一电极横向或平行地与第二电极重叠。 第一电极和第二电极垂直重叠隔离结构。 结果，泄漏电流被减轻或消除，从而提高了集成电路器件的可靠性和性能。
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