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    Memory Access Tracking Using a Peripheral Device
    5.
    发明申请
    Memory Access Tracking Using a Peripheral Device 有权

    公开(公告)号：US20230133439A1

    公开(公告)日：2023-05-04

    申请号：US17536141

    申请日：2021-11-29

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ran Avraham Koren ,  Ariel Shahar ,  Liran Liss ,  Gabi Liron ,  Aviad Shaul Yehezkel

    IPC: G06F12/0882 ,  G06F12/0831 ,  G06F13/16

    Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.

    Cache Management using Groups Partitioning
    7.
    发明公开
    Cache Management using Groups Partitioning 审中-公开

    公开(公告)号：US20240012762A1

    公开(公告)日：2024-01-11

    申请号：US17887458

    申请日：2022-08-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Gal Yefet ,  Yamin Friedman ,  Daniil Provotorov ,  Ariel Shahar ,  Natan Oppenheimer ,  Ran Avraham Koren ,  Av Urman

    IPC: G06F12/0891

    CPC classification number: G06F12/0891 ,  G06F2212/60

    Abstract: An apparatus for cache management includes an interface and a processor. The interface is for communicating with a cache memory configured to store data items. The cache controller is configured to obtain a classification of the data items into a plurality of groups, to obtain respective target capacities for at least some of the groups, each target capacity defining a respective required size of a portion of the cache memory that is permitted to be occupied by the data items belonging to the group, and to cache new data items in the cache memory, or evict cached data items from the cache memory, in accordance with a policy that complies with the target capacities specified for the groups.

    INTELLIGENT EXPOSURE OF HARDWARE LATENCY STATISTICS WITHIN AN ELECTRONIC DEVICE OR SYSTEM
    9.
    发明申请
    INTELLIGENT EXPOSURE OF HARDWARE LATENCY STATISTICS WITHIN AN ELECTRONIC DEVICE OR SYSTEM 有权

    公开(公告)号：US20250036503A1

    公开(公告)日：2025-01-30

    申请号：US18916370

    申请日：2024-10-15

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

    IPC: G06F11/07

    Abstract: A method includes presenting, by a processing device, in a user interface of a display device, a set of menu items associated with a plurality of criteria and detecting one or more input signals from one or more selections of the set of menu items. The method includes creating a command that includes one or more criteria corresponding to selected options of the plurality of criteria derived from the one or more input signals. The method includes sending, by the processing device, the command to a network adapter device to trigger a polling operation to be performed that causes internal logic of the network adapter device to sample event data associated with a latency of data packets sent by a hardware process that is specific to the one or more criteria.

    Intelligent exposure of hardware latency statistics within an electronic device or system
    10.
    发明授权
    Intelligent exposure of hardware latency statistics within an electronic device or system 有权

    公开(公告)号：US12158795B2

    公开(公告)日：2024-12-03

    申请号：US18074751

    申请日：2022-12-05

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

    IPC: G06F1/04 ,  G06F11/07

    Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

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