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公开(公告)号：US20230273669A1
公开(公告)日：2023-08-31
申请号：US18312404
申请日：2023-05-04
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Alok Kumar Mathur
IPC: G06F1/3287 , G06F3/01
CPC classification number: G06F1/3287 , G06F3/017 , G06F3/011
Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.
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公开(公告)号：US12093101B2
公开(公告)日：2024-09-17
申请号：US17682917
申请日：2022-02-28
Applicant: Meta Platforms Technologies, LLC
Inventor： Vlad Fruchter , Nishant Sitapara , Javid Jaffari , Shrirang Madhav Yardi , Bardia Zandian
CPC classification number: G06F1/28 , G02B27/017 , G05F1/66
Abstract: Systems and methods for peak power control include control circuitry which identifies a condition for a device. The control circuitry can apply the condition for the device to one or more models maintained for a plurality of device processing units of the device to determine one or more performance characteristics for the plurality of processing units. The control circuitry can distribute power credits to the plurality of device processing units of the device according to the determined performance characteristics for the plurality of device processing units, to manage a respective peak power for each respective device processing unit according to a number of the power credits distributed to the respective device processing unit.
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3.发明公开公开(公告)号：US20240231091A1
公开(公告)日：2024-07-11
申请号：US18410539
申请日：2024-01-11
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Dinesh Patil , Neeraj Upasani
IPC: G02B27/01 , G06F1/3296 , G06T19/00
CPC classification number: G02B27/017 , G06F1/3296 , G06T19/006
Abstract: A system on a chip (SoC) comprises SoC memory; one or more processor subsystems, wherein each processor subsystem includes a processor connected to the SoC memory; and a low power subsystem integrated as a separate subsystem in the SoC, wherein the low power subsystem includes a microcontroller and a power management unit (PMU), wherein the microcontroller executes a real-time operating system (RTOS), wherein the PMU is connected to each processor subsystem, the PMU operating under the control of the microcontroller to control the power to each processor subsystem.
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公开(公告)号：US20230252156A1
公开(公告)日：2023-08-10
申请号：US18296870
申请日：2023-04-06
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Neeraj Upasani , Dinesh Patil
CPC classification number: G06F21/575 , G06F1/04 , G06F21/552 , G06F21/62 , G06F21/74 , G06F21/64 , G06F2221/034 , G06F3/011
Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.
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公开(公告)号：US12248346B1
公开(公告)日：2025-03-11
申请号：US18525102
申请日：2023-11-30
Applicant: Meta Platforms Technologies, LLC
Inventor： Bardia Zandian , Eugene Gorbatov , Pankaj Raghuvanshi , Shrirang Madhav Yardi
Abstract: A method by a computing system associated with a set of disjoint devices that includes at least one wearable device includes receiving a request to perform a task. The method further includes determining, based on sensor data associated with the set of disjoint devices, a thermal-constraint differential for each device of the set of disjoint devices. The method further includes determining a plurality of workload assignments needed to be performed to accomplish the task. The method further includes distributing, based on the thermal-constraint differentials of the set of disjoint devices, the plurality of workload assignments to one or more devices of the set of disjoint devices to satisfy one or more power or thermal constraints associated with each device of the set of disjoint devices. The method further includes performing the task by causing the one or more devices to execute the distributed plurality of work assignments.
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Patent Agency Ranking
公开(公告)号：US20240231471A1
公开(公告)日：2024-07-11
申请号：US18410552
申请日：2024-01-11
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Dinesh Patil , Neeraj Upasani
IPC: G06F1/3293
CPC classification number: G06F1/3293
Abstract: A system on a chip (SoC) comprises SoC memory; one or more processor subsystems, wherein each processor subsystem includes a processor connected to the SoC memory; and a low power subsystem integrated as a separate subsystem in the SoC, wherein the low power subsystem includes a microcontroller and a power management unit (PMU), wherein the microcontroller executes a real-time operating system (RTOS), wherein the PMU is connected to each processor subsystem, the PMU operating under the control of the microcontroller to control the power to each processor subsystem, wherein the low power subsystem is configured to boot up the SoC via the microcontroller executing out of SoC memory.
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公开(公告)号：US12032839B2
公开(公告)日：2024-07-09
申请号：US16947432
申请日：2020-07-31
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Gregory Edward Ehmann , Ennio Salemi , George Spatz , Jeffrey Ryden
CPC classification number: G06F3/0634 , G06F1/28 , G06F3/0625 , G06F3/064 , G06F3/0673 , G06T19/006 , G06F3/011
Abstract: The disclosure describes techniques for hierarchical power management of memory of an artificial reality system to reduce power consumption by the memory. An example device may be a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content for display. The device includes memory divided into multiple memory blocks configurable to operate in a plurality of power modes. The device also includes memory block controllers controlling memory blocks. Each memory block controller controls which power mode in which the corresponding memory block is to operate, independent of any of the other memory blocks. The device includes a memory power controller configured to configure control registers of the memory block controllers to direct the memory block controllers to select one of the plurality of power modes for the memory blocks when the memory blocks are not being accessed.
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公开(公告)号：US20240146548A1
公开(公告)日：2024-05-02
申请号：US17933892
申请日：2022-09-21
Applicant: Meta Platforms Technologies, LLC
Inventor： Sudhir Satpathy , Renji George Thomas , Shrirang Madhav Yardi
CPC classification number: H04L9/3278 , H04L9/0866 , H04L9/30
Abstract: A testing system includes one or more processors; and a memory storing instructions that, when executed, cause the one or more processors to: perform, on each array of an SRAM of a System-on-a-Chip (SoC), the SRAM having a plurality of arrays, one or more tests to determine one or more biased cells in the array, generate bias characteristics for each array of the SRAM based on the one or more biased cells of the array, compare bias characteristics of each of the plurality of arrays, select, based on the comparison, an array of the plurality of arrays as a Physically Unclonable Function (PUF) array, and store an identifier of the PUF array into a memory of the SoC.
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9.发明公开公开(公告)号：US20240095376A1
公开(公告)日：2024-03-21
申请号：US17933897
申请日：2022-09-21
Applicant: Meta Platforms Technologies, LLC
Inventor： Sudhir Satpathy , Renji George Thomas , Shrirang Madhav Yardi
CPC classification number: G06F21/602 , G06F21/554 , G06F21/64 , G06F2221/0755
Abstract: An example method includes identifying, by processing circuitry, a Physically Unclonable Function (PUF) array selected from a static random-access memory (SRAM) device of a System-on-a-Chip (SoC); reading, by the processing circuitry, from a memory, helper data associated with the PUF array and usable for generating a cryptographic key based on the PUF array; determining, by the processing circuitry, whether the helper data associated with the PUF array has been altered after its initial generation by a test system; and in response to determining that the helper data associated with the PUF array has been altered, disabling access to data, software, or functions protected by the cryptographic key generated based on the PUF array.
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公开(公告)号：US11636210B2
公开(公告)日：2023-04-25
申请号：US17009512
申请日：2020-09-01
Applicant: Meta Platforms Technologies, LLC
Inventor： Shrirang Madhav Yardi , Neeraj Upasani , Dinesh Patil
IPC: G06F15/177 , G06F9/00 , G06F21/57 , G06F1/04 , G06F21/55 , G06F21/62 , G06F21/74 , G06F21/64 , G06F3/01
Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.
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