公开(公告)号：US20230273669A1

公开(公告)日：2023-08-31

申请号：US18312404

申请日：2023-05-04

Applicant: Meta Platforms Technologies, LLC

Inventor： Shrirang Madhav Yardi ,  Alok Kumar Mathur

IPC: G06F1/3287 ,  G06F3/01

CPC classification number: G06F1/3287 ,  G06F3/017 ,  G06F3/011

Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.

公开(公告)号：US11670364B2

公开(公告)日：2023-06-06

申请号：US17303084

申请日：2021-05-19

Applicant: Meta Platforms Technologies, LLC

Inventor： Daniel Henry Morris ,  Alok Kumar Mathur

IPC: G11C11/417 ,  G11C5/14 ,  G11C11/4074 ,  H03K17/16

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C11/4074 ,  H03K17/165

Abstract: System on a Chip (SoC) integrated circuits are configured to reduce Static Random-Access Memory (SRAM) power leakage. For example, SoCs configured to reduce SRAM power leakage may form part of an artificial reality system including at least one head mounted display. Power switching logic on the SoC includes a first power gating transistor that supplies a first, higher voltage to an SRAM array when the SRAM array is in an active state, and a third power gating transistor that isolates a second power gating transistor from the first, higher voltage when the SRAM array is in the active state. The second power gating transistor further supplies a second, lower voltage to the SRAM array when the SRAM array is in a deep retention state, such that SRAM power leakage is reduced in the deep retention state.

公开(公告)号：US12072752B2

公开(公告)日：2024-08-27

申请号：US18312404

申请日：2023-05-04

Applicant: Meta Platforms Technologies, LLC

Inventor： Shrirang Madhav Yardi ,  Alok Kumar Mathur

IPC: G06F1/32 ,  G06F1/3287 ,  G06F3/01 ,  G06F15/78

CPC classification number: G06F1/3287 ,  G06F3/011 ,  G06F3/017

Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.

公开(公告)号：US11868281B2

公开(公告)日：2024-01-09

申请号：US17818196

申请日：2022-08-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Alok Kumar Mathur ,  Ennio Salemi ,  Drew Eric Wingard ,  Valerio Catalano

IPC: G06F13/16 ,  G06T19/00 ,  G02B27/01 ,  G06F3/01 ,  G06V20/20

CPC classification number: G06F13/1626 ,  G02B27/0172 ,  G06F3/011 ,  G06F13/161 ,  G06F13/1642 ,  G06T19/006 ,  G06V20/20

Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.

公开(公告)号：US11700496B2

公开(公告)日：2023-07-11

申请号：US17535805

申请日：2021-11-26

Applicant: Meta Platforms Technologies, LLC

Inventor： Alok Kumar Mathur

IPC: H04R3/00 ,  H04R29/00 ,  H04R1/40

CPC classification number: H04R29/005 ,  H04R1/406 ,  H04R3/005

Abstract: This disclosure describes techniques that include aligning processing of audio samples collected by multiple audio sensors or microphones. In one example, this disclosure describes a method comprising detecting a transition by the second microphone from a disabled state to an enabled state; after detecting the transition, performing phase alignment between audio samples collected by the first microphone and audio samples collected by the second microphone by introducing a delay in starting processing of the audio samples collected by the second microphone; and processing the phase-aligned audio samples.

公开(公告)号：US11675415B2

公开(公告)日：2023-06-13

申请号：US17647946

申请日：2022-01-13

Applicant: Meta Platforms Technologies, LLC

Inventor： Shrirang Madhav Yardi ,  Alok Kumar Mathur

IPC: G06F1/3287 ,  G06F3/01

CPC classification number: G06F1/3287 ,  G06F3/011 ,  G06F3/017

Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.

公开(公告)号：US20220391331A1

公开(公告)日：2022-12-08

申请号：US17818196

申请日：2022-08-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Alok Kumar Mathur ,  Ennio Salemi ,  Drew Eric Wingard ,  Valerio Catalano

IPC: G06F13/16 ,  G06T19/00 ,  G02B27/01 ,  G06F3/01 ,  G06V20/20

Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.

公开(公告)号：US20220375511A1

公开(公告)日：2022-11-24

申请号：US17303084

申请日：2021-05-19

Applicant: Meta Platforms Technologies, LLC

Inventor： Daniel Henry Morris ,  Alok Kumar Mathur

IPC: G11C11/417 ,  G11C11/4074 ,  G11C5/14 ,  H03K17/16

Abstract: System on a Chip (SoC) integrated circuits are configured to reduce Static Random-Access Memory (SRAM) power leakage. For example, SoCs configured to reduce SRAM power leakage may form part of an artificial reality system including at least one head mounted display. Power switching logic on the SoC includes a first power gating transistor that supplies a first, higher voltage to an SRAM array when the SRAM array is in an active state, and a third power gating transistor that isolates a second power gating transistor from the first, higher voltage when the SRAM array is in the active state. The second power gating transistor further supplies a second, lower voltage to the SRAM array when the SRAM array is in a deep retention state, such that SRAM power leakage is reduced in the deep retention state.