公开(公告)号：US20220083241A1

公开(公告)日：2022-03-17

申请号：US16948426

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Walter Di Francesco ,  Yuanhang Cao ,  Luca De Santis ,  Fumin Gu

IPC: G06F3/06

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

公开(公告)号：US11775185B2

公开(公告)日：2023-10-03

申请号：US16948426

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Walter Di Francesco ,  Yuanhang Cao ,  Luca De Santis ,  Fumin Gu

IPC: G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679 ,  G06F9/505 ,  G06F9/5094 ,  G06F2209/5018

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

公开(公告)号：US20230195312A1

公开(公告)日：2023-06-22

申请号：US17990126

申请日：2022-11-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Fumin Gu ,  John Paul Aglubat

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0679

Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include causing a memory die to be placed in a suspended state to suspend execution of a first media access operation with a reserved current budget, receiving a set of requests to execute at least a second media access operation during the suspended state, and in response receiving the set of requests, handling the set of requests by implementing current budget arbitration logic with respect to the reserved current budget.

公开(公告)号：US20240272812A1

公开(公告)日：2024-08-15

申请号：US18621747

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

公开(公告)号：US11977748B2

公开(公告)日：2024-05-07

申请号：US17668311

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

公开(公告)号：US20230084630A1

公开(公告)日：2023-03-16

申请号：US17668311

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.