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公开(公告)号：US11928347B2
公开(公告)日：2024-03-12
申请号：US18114967
申请日：2023-02-27
发明人： Kishore Kumar Muchherla , Mustafa N Kaynak , Peter Feeley , Sampath K Ratnam , Shane Nowell , Sivagnanam Parthasarathy , Karl D Schuh , Jiangang Wu
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/064 , G06F3/0679 , G11C16/26
摘要： A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.
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公开(公告)号：US11593005B2
公开(公告)日：2023-02-28
申请号：US17219489
申请日：2021-03-31
发明人： Kishore Kumar Muchherla , Mustafa N Kaynak , Peter Feeley , Sampath K Ratnam , Shane Nowell , Sivagnanam Parthasarathy , Karl D Schuh , Jiangang Wu
摘要： A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.
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公开(公告)号：US11410734B1
公开(公告)日：2022-08-09
申请号：US17219498
申请日：2021-03-31
发明人： Kishore Kumar Muchherla , Sampath K Ratnam , Shane Nowell , Sivagnanam Parthasarathy , Mustafa N Kaynak , Karl D Schuh , Peter Feeley , Jiangang Wu
摘要： A processing device of a memory sub-system is configured to detect a power on event associated with the memory device; scan one or more blocks of a plurality of blocks of the memory device to determine a corresponding time after program (TAP) associated with each block of the one or more blocks; estimate, based on the corresponding TAP of the each block of the one or more blocks, a duration of a power off state preceding the power on event; and update voltage bin assignments of the plurality of blocks associated with the memory device based on the duration of the power off state.
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