公开(公告)号：US10217706B2

公开(公告)日：2019-02-26

申请号：US15685907

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani ,  Kyle Armstrong ,  Michael D. Hyatt ,  Michael Dean Van Patten ,  David A. Kewley ,  Ming-Chuan Yang

IPC: H01L23/525 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

公开(公告)号：US20170352616A1

公开(公告)日：2017-12-07

申请号：US15685907

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani ,  Kyle Armstrong ,  Michael D. Hyatt ,  Michael Dean Van Patten ,  David A. Kewley ,  Ming-Chuan Yang

IPC: H01L23/525 ,  H01L23/532 ,  H01L23/528 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L23/525 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

公开(公告)号：US09048292B2

公开(公告)日：2015-06-02

申请号：US13660860

申请日：2012-10-25

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani ,  Kyle Armstrong ,  Michael D. Hyatt ,  Michael Dean Van Patten ,  David A. Kewley ,  Ming-Chuan Yang

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L23/525 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract translation: 一些实施例包括形成导电线的方法。 光致抗蚀剂特征形成在衬底上，其中至少一个光致抗蚀剂特征具有变窄的区域。 修整光致抗蚀剂特征，其穿过狭窄区域以形成间隙。 隔板沿光致抗蚀剂特征的侧壁形成。 间隙中的两个垫片合并在一起。 去除光致抗蚀剂特征以留下包括间隔物的图案。 该图案延伸到衬底中以在衬底内形成多个凹槽。 导电材料形成在凹槽内以形成导电线。 一些实施例包括在半导体衬底上具有多条线的半导体结构。 两条线彼此相邻并且基本上彼此平行，除了在所述两条线彼此合并的区域中。

公开(公告)号：US08745545B2

公开(公告)日：2014-06-03

申请号：US14037049

申请日：2013-09-25

Applicant: Micron Technology, Inc.

Inventor： Ming-Chuan Yang ,  Jung H. Woo

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70125 ,  G03F7/70441 ,  G03F7/705

Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

Abstract translation: 公开了用于诸如半导体制造的光刻工艺的掩模工艺变化性的随机模型的系统和方法。 在一个实施例中，随机误差模型可以基于掩模处理误差的概率分布。 随机误差模型可以产生具有随机误差的多个掩模布局，诸如接触的随机和非均匀变化。 在其他实施例中，随机模型可以应用于临界尺寸均匀性（CDU）优化或设计规则（DR）复杂度。

公开(公告)号：US20140117529A1

公开(公告)日：2014-05-01

申请号：US13660860

申请日：2012-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sipani ,  Kyle Armstrong ,  Michael D. Hyatt ,  Michael Dean Van Patten ,  David A. Kewley ,  Ming-Chuan Yang

IPC: H01L21/32 ,  H01L23/48 ,  H01L23/58 ,  H01L21/22 ,  H01L21/768

CPC classification number: H01L23/525 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract translation: 一些实施例包括形成导电线的方法。 光致抗蚀剂特征形成在衬底上，其中至少一个光致抗蚀剂特征具有变窄的区域。 修整光致抗蚀剂特征，其穿过狭窄区域以形成间隙。 隔板沿光致抗蚀剂特征的侧壁形成。 间隙中的两个垫片合并在一起。 去除光致抗蚀剂特征以留下包括间隔物的图案。 该图案延伸到衬底中以在衬底内形成多个凹槽。 导电材料形成在凹槽内以形成导电线。 一些实施例包括在半导体衬底上具有多条线的半导体结构。 两条线彼此相邻并且基本上彼此平行，除了在所述两条线彼此合并的区域中。

公开(公告)号：US10424506B2

公开(公告)日：2019-09-24

申请号：US15973784

申请日：2018-05-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler G. Hansen ,  Ming-Chuan Yang ,  Vishal Sipani

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311 ,  H01L23/535 ,  H01L23/532

Abstract: Integrated circuits, as well as methods of their formation, include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.

公开(公告)号：US09123722B2

公开(公告)日：2015-09-01

申请号：US14177030

申请日：2014-02-10

Applicant: Micron Technology, Inc.

Inventor： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract translation: 一些实施例包括形成互连的方法。 可以形成第一电路电平，并且可以在这样的第一电平上形成第一电介质区域。 可以在第一介电区域上形成第二级别的电路。 可以形成互连以延伸穿过这样的第二级。 可以在第二电平层上形成第二电介质区域，并且可以在第二电介质区域上形成第三电平的电路。 第三级电路可以通过互连电连接到第一级电路。 一些实施例包括具有从电路的第一电平延伸通过第二电平电平的开口到第三电平电平的互连的结构; 具有包括多个单独的导电柱的单独互连。

公开(公告)号：US20140151902A1

公开(公告)日：2014-06-05

申请号：US14177030

申请日：2014-02-10

Applicant: Micron Technology, Inc.

Inventor： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract translation: 一些实施例包括形成互连的方法。 可以形成第一电路电平，并且可以在这样的第一电平上形成第一电介质区域。 可以在第一介电区域上形成第二级别的电路。 可以形成互连以延伸穿过这样的第二级。 可以在第二电平层上形成第二电介质区域，并且可以在第二电介质区域上形成第三电平的电路。 第三级电路可以通过互连电连接到第一级电路。 一些实施例包括具有从电路的第一电平延伸通过第二电平电平的开口到第三电平电平的互连的结构; 具有包括多个单独的导电柱的单独互连。

公开(公告)号：US20130164944A1

公开(公告)日：2013-06-27

申请号：US13769473

申请日：2013-02-18

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani ,  Baosuo Zhou ,  Ming-Chuan Yang

IPC: H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.

Abstract translation: 一些实施例包括形成开口的方法。 例如，结构可以具有多条导电线上的材料。 可以在材料上方形成多个环形特征，其中环形特征与线交叉。 图案化的掩模可以形成在环形特征上，其中图案化掩模留下通过图案化掩模中的窗口暴露的环形特征的段。 环形特征的暴露部分可以限定多个开口，并且这样的开口可以被转移到材料中以形成延伸到导电线的开口。

公开(公告)号：US10741445B2

公开(公告)日：2020-08-11

申请号：US16520445

申请日：2019-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler G. Hansen ,  Ming-Chuan Yang ,  Vishal Sipani

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/535 ,  H01L23/532

Abstract: Integrated circuits include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.