公开(公告)号：US11764152B1

公开(公告)日：2023-09-19

申请号：US17714797

申请日：2022-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harunobu Kondo ,  Kazuteru Ishizuka ,  Wataru Nobehara ,  Ryosuke Yatsushiro ,  Makoto Saito

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226

Abstract: Disclosed herein is an apparatus that includes a semiconductor substrate having a main surface extending in a first direction and a second direction different from the first direction and a conductive pattern formed over the main surface of the semiconductor substrate. The conductive pattern includes a first section extending in the first direction, a second section extending in the second direction, and a third section connected between the first and second sections. The third section of the conductive pattern has a first slit extending in a third direction different from the first and second directions.

公开(公告)号：US10950277B1

公开(公告)日：2021-03-16

申请号：US16656907

申请日：2019-10-18

Applicant: Micron Technology, Inc.

Inventor： Wataru Nobehara ,  Takamitsu Onda

IPC: G11C5/00 ,  G11C5/06 ,  G11C5/02

Abstract: An integrated circuit including a signal line layout is disclosed. A signal line layout may include a number of signal lines configured for conveying a number of signals. The signal line layout may further include a number of shield lines. Each signal line of the number of signal lines may be positioned adjacent a first shield line and a second shield line of the number of the shield lines. Further, first shield line may extend a length of an adjacent signal line and the second shield line may extend less than a length of the adjacent signal line. An electronic system including circuitry having one or more signal line layouts, and methods of forming signal line layout are also described.

公开(公告)号：US11742281B2

公开(公告)日：2023-08-29

申请号：US17154871

申请日：2021-01-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Takashi Ishihara ,  Wataru Nobehara

IPC: H01L23/522 ,  H01L23/00 ,  H01L27/02 ,  H01L27/105

CPC classification number: H01L23/5222 ,  H01L24/09 ,  H01L27/0266 ,  H01L27/0292 ,  H01L27/105 ,  H01L2224/02331

Abstract: A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL).

公开(公告)号：US20210257291A1

公开(公告)日：2021-08-19

申请号：US17154871

申请日：2021-01-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Takashi Ishihara ,  Wataru Nobehara

IPC: H01L23/522 ,  H01L23/00 ,  H01L27/02 ,  H01L27/105

Abstract: A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL).

公开(公告)号：US20230326852A1

公开(公告)日：2023-10-12

申请号：US17714797

申请日：2022-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harunobu Kondo ,  Kazuteru Ishizuka ,  Wataru Nobehara ,  Ryosuke Yatsushiro ,  Makoto Saito

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226

Abstract: Disclosed herein is an apparatus that includes a semiconductor substrate having a main surface extending in a first direction and a second direction different from the first direction and a conductive pattern formed over the main surface of the semiconductor substrate. The conductive pattern includes a first section extending in the first direction, a second section extending in the second direction, and a third section connected between the first and second sections. The third section of the conductive pattern has a first slit extending in a third direction different from the first and second directions.

公开(公告)号：US10916497B2

公开(公告)日：2021-02-09

申请号：US16144615

申请日：2018-09-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Takashi Ishihara ,  Wataru Nobehara

IPC: H01L23/522 ,  H01L27/02 ,  H01L27/105 ,  H01L23/00

Abstract: A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL).