公开(公告)号：US20020175370A1

公开(公告)日：2002-11-28

申请号：US09861638

申请日：2001-05-22

Applicant: MOTOROLA, INC.

Inventor： David E. Bockelman

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC classification number: H01L29/267 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/8258 ,  H01L27/0605

Abstract: A hybrid semiconductor structure is provided. The structure may comprise a field effect transistor that may include a back gate. The back gate for a non-compound semiconductor field effect transistor may be formed by providing a contact (506, 550) over a compound semiconductor region before forming an insulating layer (205, 508, 542, 1161) and before forming the body of the field effect transistor over the compound semiconductor region. If desired, a contact (528, 544) for a back gate may also be formed after the body of the non-compound semiconductor field effect transistor is formed by forming a trench (526, 548) and depositing the contact (528, 544) in the trench (526, 548). In forming the back gate, the insulating layer (205, 508, 542, 1161) may be used as an etch-stop.

Abstract translation: 提供了一种混合半导体结构。 该结构可以包括可以包括背栅的场效应晶体管。 用于非化合物半导体场效应晶体管的背栅可以通过在形成绝缘层（205,508,542,1161）之前在化合物半导体区域上提供接触（506,550）并且在形成绝缘层 场效应晶体管在化合物半导体区域上。 如果需要，还可以在通过形成沟槽（526,548）形成非化合物半导体场效应晶体管的主体并且沉积接触件（528,544）之后，形成用于背栅的触点（528,544） 在沟槽（526,548）中。 在形成背栅时，可以将绝缘层（205,508,542,1161）用作蚀刻停止。

公开(公告)号：US20030020086A1

公开(公告)日：2003-01-30

申请号：US09911456

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Robert E. Stengel ,  Edgar H. Callaway JR. ,  David E. Bockelman

IPC: H01L033/00

CPC classification number: H01L27/0688 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/15 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0261 ,  H01S2301/173 ,  H01L2224/80001

Abstract: A process and a semiconductor structure are disclosed for fabricating substantially identical tuned ferro-electric components for varying the frequency or phase of a radio frequency signal at multiple locations of an integrated circuit using the same control voltage. The process includes the steps of epitaxially forming a monocrystalline layer of ferro-electric material on a monocrystalline ground plane; forming an input electrically coupled to the monocrystalline layer of ferro-electric material for receiving a bias voltage to vary at least one of a frequency and a phase of a radio frequency signal; epitaxially forming a monocrystalline layer of an electrically conductive material on the monocrystalline layer of ferro-electric material to constitute a transmission line; and forming an input electrically coupled to the transmission line for receiving the radio frequency signal.

Abstract translation: 公开了一种工艺和半导体结构，用于制造基本相同的调谐铁电部件，用于使用相同的控制电压来改变集成电路的多个位置处的射频信号的频率或相位。 该方法包括在单晶地平面上外延形成铁电材料的单晶层的步骤; 形成电耦合到所述铁电材料的单晶层的输入端，用于接收偏置电压以改变射频信号的频率和相位中的至少一个; 外延地在铁电材料的单晶层上形成导电材料的单晶层以构成传输线; 以及形成电耦合到所述传输线的用于接收所述射频信号的输入。

公开(公告)号：US20030020090A1

公开(公告)日：2003-01-30

申请号：US09911491

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Joseph P. Heck ,  David E. Bockelman ,  Robert E. Stengel

IPC: H01L029/74

CPC classification number: H01L21/8221 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/15 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0261 ,  H01S2301/173 ,  H03F1/18 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. Devices may be formed in the silicon wafer prior to growing the high quality epitaxial layers. Then, to achieve the formation of a compliant substrate, an accommodating buffer layer is grown on silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Compound devices are then formed on the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Silicon devices and circuits (e.g., CMOS circuits) in the silicon wafer are wired to the compound devices (e.g., MESFETs, HBTs, HEMTs, PHEMTs, etc.), forming an electrical connection therebetween.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 可以在生长高质量外延层之前在硅晶片中形成器件。 然后，为了形成顺应性衬底，在硅晶片上生长容纳缓冲层。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 然后在覆盖的单晶层上形成复合器件。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 硅晶片中的硅器件和电路（例如，CMOS电路）被连接到复合器件（例如，MESFET，HBT，HEMT，PHEMT等），在它们之间形成电连接。

公开(公告)号：US20030020103A1

公开(公告)日：2003-01-30

申请号：US09911448

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Edgar H. Callaway JR. ,  Robert E. Stengel ,  David E. Bockelman

IPC: H01L029/74 ,  H01L031/112 ,  H01L021/84

CPC classification number: H01L29/66856 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/812

Abstract: A composite semiconductor including silicon and compound semiconductor, and having a metal semiconductor field effect transistor (MESFET) integrated at least partially with the silicon and at least partially with the GaAs having a silicon back gate is provided. The back gate for the MESFET may be formed by doping a region of the monocrystalline silicon substrate before forming the transistor. In a structure according the invention, integrated circuits may be provided to match the threshold voltages of one MESFET to another, improve the transconductance of a MESFET, and improve the switching speed of a MESFET.

Abstract translation: 提供了包括硅和化合物半导体的复合半导体，并且具有至少部分地与硅并且至少部分地与具有硅背栅的GaAs集成的金属半导体场效应晶体管（MESFET）。 用于MESFET的背栅可以通过在形成晶体管之前掺杂单晶硅衬底的区域来形成。 在根据本发明的结构中，可以提供集成电路以将一个MESFET的阈值电压与另一个MESFET的阈值电压相匹配，改善MESFET的跨导，并提高MESFET的开关速度。