公开(公告)号：US20030034505A1

公开(公告)日：2003-02-20

申请号：US09930260

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Robert E. Stengel ,  Edgar H. Callaway JR.

IPC: H01L031/0328

CPC classification number: H01L21/02488 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02505 ,  H01L21/02521 ,  H01L21/31691

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Enhancement of thermal conductivity of the monocrystalline oxide layer is accomplished with the use of isotopically enriched materials.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 通过使用同位素富集的材料来实现单晶氧化物层的导热性的提高。

公开(公告)号：US20030020103A1

公开(公告)日：2003-01-30

申请号：US09911448

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Edgar H. Callaway JR. ,  Robert E. Stengel ,  David E. Bockelman

IPC: H01L029/74 ,  H01L031/112 ,  H01L021/84

CPC classification number: H01L29/66856 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/812

Abstract: A composite semiconductor including silicon and compound semiconductor, and having a metal semiconductor field effect transistor (MESFET) integrated at least partially with the silicon and at least partially with the GaAs having a silicon back gate is provided. The back gate for the MESFET may be formed by doping a region of the monocrystalline silicon substrate before forming the transistor. In a structure according the invention, integrated circuits may be provided to match the threshold voltages of one MESFET to another, improve the transconductance of a MESFET, and improve the switching speed of a MESFET.

Abstract translation: 提供了包括硅和化合物半导体的复合半导体，并且具有至少部分地与硅并且至少部分地与具有硅背栅的GaAs集成的金属半导体场效应晶体管（MESFET）。 用于MESFET的背栅可以通过在形成晶体管之前掺杂单晶硅衬底的区域来形成。 在根据本发明的结构中，可以提供集成电路以将一个MESFET的阈值电压与另一个MESFET的阈值电压相匹配，改善MESFET的跨导，并提高MESFET的开关速度。

公开(公告)号：US20030020086A1

公开(公告)日：2003-01-30

申请号：US09911456

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Robert E. Stengel ,  Edgar H. Callaway JR. ,  David E. Bockelman

IPC: H01L033/00

CPC classification number: H01L27/0688 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/15 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0261 ,  H01S2301/173 ,  H01L2224/80001

Abstract: A process and a semiconductor structure are disclosed for fabricating substantially identical tuned ferro-electric components for varying the frequency or phase of a radio frequency signal at multiple locations of an integrated circuit using the same control voltage. The process includes the steps of epitaxially forming a monocrystalline layer of ferro-electric material on a monocrystalline ground plane; forming an input electrically coupled to the monocrystalline layer of ferro-electric material for receiving a bias voltage to vary at least one of a frequency and a phase of a radio frequency signal; epitaxially forming a monocrystalline layer of an electrically conductive material on the monocrystalline layer of ferro-electric material to constitute a transmission line; and forming an input electrically coupled to the transmission line for receiving the radio frequency signal.

Abstract translation: 公开了一种工艺和半导体结构，用于制造基本相同的调谐铁电部件，用于使用相同的控制电压来改变集成电路的多个位置处的射频信号的频率或相位。 该方法包括在单晶地平面上外延形成铁电材料的单晶层的步骤; 形成电耦合到所述铁电材料的单晶层的输入端，用于接收偏置电压以改变射频信号的频率和相位中的至少一个; 外延地在铁电材料的单晶层上形成导电材料的单晶层以构成传输线; 以及形成电耦合到所述传输线的用于接收所述射频信号的输入。

公开(公告)号：US20030022456A1

公开(公告)日：2003-01-30

申请号：US09911445

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Edgar H. Callaway JR.

IPC: H01L029/04

CPC classification number: G06F1/105 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/132 ,  G02B6/43 ,  G02B2006/12061 ,  H01L27/15 ,  H01L31/173 ,  H01S5/021 ,  H01S5/026 ,  H01S5/0261 ,  H01S5/183 ,  H01S5/423 ,  H01S2301/173

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying a monocrystalline substrate of a semiconductor structure by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. An optical waveguide is formed in a monocrystalline layer grown on the semiconductor structure for distributing an optical signal to a selected portion of circuitry formed in the semiconductor structure. An optical source is formed in the semiconductor structure and coupled to the optical waveguide for generating the optical signal. A waveguide interferometer is formed in a monocrystalline layer of the semiconductor structure and coupled to the optical waveguide for switching the optical signal between an nullonnull state and an nulloffnull state. An optical detector is formed in the semiconductor structure and coupled to the waveguide interferometer for converting the optical signal to an electrical signal at the selected portion of circuitry of the semiconductor structure.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在半导体结构的单晶衬底上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 光波导形成在半导体结构上生长的单晶层中，用于将光信号分配到在半导体结构中形成的电路的选定部分。 在半导体结构中形成光源并耦合到光波导以产生光信号。 波导干涉仪形成在半导体结构的单晶层中并且耦合到光波导，用于在“接通”状态和“断开”状态之间切换光信号。 光学检测器形成在半导体结构中并耦合到波导干涉仪，用于将光信号转换成在半导体结构的电路的选定部分处的电信号。

公开(公告)号：US20030010998A1

公开(公告)日：2003-01-16

申请号：US09900882

申请日：2001-07-10

Applicant: MOTOROLA, INC.

Inventor： Edgar H. Callaway JR.

IPC: H01L031/0328

CPC classification number: H01L27/0605 ,  H01L21/8258

Abstract: Apparatus and techniques for implementing wireless communication between integrated transmitters and integrated receivers are provided. By providing a semiconductor structure including silicon and a compound semiconductor, a single circuit can be integrated part in silicon and part in compound semiconductor. In a semiconductor structure according to the invention, a wireless transmitter and a wireless receiver can be integrated in a compound semiconductor portion of the structure and digital CMOS circuitry can be integrated in the silicon portion of the structure. This obtains substantially increased wireless transmission efficiency. The circuits according to the invention can be implemented with circuits that wirelessly transmit from one portion of the chip to another portion of the chip, or with circuits that wirelessly transmit from one integrated circuit to a second integrated circuit.

Abstract translation: 提供了用于实现集成发射机和集成接收机之间的无线通信的装置和技术。 通过提供包括硅和化合物半导体的半导体结构，单个电路可以集成在硅中并且部分在化合物半导体中。 在根据本发明的半导体结构中，无线发射器和无线接收器可以集成在该结构的复合半导体部分中，并且数字CMOS电路可以集成在该结构的硅部分中。 这获得了显着提高的无线传输效率。 根据本发明的电路可以用从芯片的一部分无线地从芯片的另一部分或与从一个集成电路无线地传输到第二集成电路的电路的电路来实现。

公开(公告)号：US20030030056A1

公开(公告)日：2003-02-13

申请号：US09921898

申请日：2001-08-06

Applicant: MOTOROLA, INC.

Inventor： Edgar H. Callaway JR.

IPC: H01L031/0256

CPC classification number: H01L29/66462 ,  H01L21/8258 ,  H01L27/0605 ,  H03F3/345

Abstract: Reference circuits are provided that include circuit components formed from both a composite semiconductor and silicon on a single integrated circuit. The reference circuits provide a reference current that is a function of the threshold voltage of the compound semiconductor device. The reference circuits may include, for example, a HEMT formed on a gallium arsenide layer, which overlays at least a portion of a silicon substrate. A MOSFET formed on the silicon substrate is coupled to the HEMT through a current mirror so that both devices are coupled to receive current based on a common current. Each device is coupled to one input of an error amplifier that provides an output signal that adjusts the common current.

Abstract translation: 提供了包括在单个集成电路上由复合半导体和硅形成的电路部件的参考电路。 参考电路提供作为化合物半导体器件的阈值电压的函数的参考电流。 参考电路可以包括例如形成在砷化镓层上的HEMT，其覆盖至少一部分硅衬底。 形成在硅衬底上的MOSFET通过电流镜耦合到HEMT，使得两个器件被耦合以基于公共电流接收电流。 每个器件耦合到误差放大器的一个输入端，该误差放大器提供调节公共电流的输出信号。

公开(公告)号：US20030027409A1

公开(公告)日：2003-02-06

申请号：US09919967

申请日：2001-08-02

Applicant: MOTOROLA, INC.

Inventor： Jamal Ramdani ,  Edgar H. Callaway JR. ,  Alexander Demkov ,  Lyndee Hilt

IPC: H01L021/20

CPC classification number: H01L21/0245 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521

Abstract: High quality epitaxial layers of germanium can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline germanium layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract translation: 通过首先在硅晶片上生长容纳缓冲层，可以生长覆盖大型硅晶片的锗的高质量外延层。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆单晶锗层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

公开(公告)号：US20030022438A1

公开(公告)日：2003-01-30

申请号：US09910798

申请日：2001-07-24

Applicant: MOTOROLA, INC.

Inventor： Edgar H. Callaway JR. ,  Kenneth D. Cornett

IPC: H01L021/8242 ,  H01L021/8234 ,  H01L021/336 ,  H01L021/00

CPC classification number: H01L29/66848 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8258 ,  H01L27/0605 ,  H01S5/021 ,  H01S5/0261 ,  H01S5/183 ,  H01S5/50 ,  H01S2301/173

Abstract: A composite semiconductor structure may be processed to form a compound semiconductor dynamic threshold-voltage field effect transistor. The compound semiconductor dynamic threshold-voltage field effect transistor may be provided by forming a compound semiconductor field effect transistor using a compound semiconductor region of the composite semiconductor structure and providing an electrical tie between a node at the gate of the transistor and a node at the body of the transistor. The node at the body may be a node that is coupled to a channel that is formed in the body when the transistor is conducting electricity. Dielectric isolation may be provided through an insulation layer that is in between the compound semiconductor region and non-compound semiconductor region of the composite semiconductor structure. Lateral isolation may be provided through trenches on the sides of the transistor that are filled with an insulator.

Abstract translation: 可以处理复合半导体结构以形成化合物半导体动态阈值电压场效应晶体管。 化合物半导体动态阈值电压场效应晶体管可以通过使用复合半导体结构的化合物半导体区域形成化合物半导体场效应晶体管并在晶体管的栅极处的节点与晶体管的节点之间提供电连接来提供 晶体管体。 身体上的节点可以是当晶体管导通电力时耦合到在体内形成的沟道的节点。 电介质隔离可以通过位于复合半导体结构的化合物半导体区域和非化合物半导体区域之间的绝缘层来提供。 可以通过填充有绝缘体的晶体管的侧面上的沟槽提供横向隔离。