公开(公告)号：US20030020090A1

公开(公告)日：2003-01-30

申请号：US09911491

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Joseph P. Heck ,  David E. Bockelman ,  Robert E. Stengel

IPC: H01L029/74

CPC classification number: H01L21/8221 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/15 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0261 ,  H01S2301/173 ,  H03F1/18 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. Devices may be formed in the silicon wafer prior to growing the high quality epitaxial layers. Then, to achieve the formation of a compliant substrate, an accommodating buffer layer is grown on silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Compound devices are then formed on the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Silicon devices and circuits (e.g., CMOS circuits) in the silicon wafer are wired to the compound devices (e.g., MESFETs, HBTs, HEMTs, PHEMTs, etc.), forming an electrical connection therebetween.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 可以在生长高质量外延层之前在硅晶片中形成器件。 然后，为了形成顺应性衬底，在硅晶片上生长容纳缓冲层。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 然后在覆盖的单晶层上形成复合器件。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 硅晶片中的硅器件和电路（例如，CMOS电路）被连接到复合器件（例如，MESFET，HBT，HEMT，PHEMT等），在它们之间形成电连接。

公开(公告)号：US20030025116A1

公开(公告)日：2003-02-06

申请号：US09918801

申请日：2001-08-01

Applicant: MOTOROLA, INC.

Inventor： Robert J. Higgins JR. ,  Barbara Foley Barenburg ,  Joseph P. Heck ,  Jonathan F. Gorrell

IPC: H01L029/04

CPC classification number: H01L29/66863 ,  G02B6/12002 ,  G02B6/12004 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691 ,  H01L21/78 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0688 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/0261 ,  H01S2301/173 ,  H01L2224/80001

Abstract: A semiconductor laminate configured for dividing into predetermined parts has a lateral expanse and includes: (a) a monocrystalline substrate substantially coterminous with the lateral expanse; (b) at least one layer including a monocrystalline compound semiconductor material; and (c) at least one intermediate layer substantially separating the substrate and the compound semiconductor material. The at least one compound semiconductor material layer is arrayed to present intervals substantially devoid of the monocrystalline compound semiconductor material that generally establish lateral limits of the predetermined parts. The method includes the steps of: (a) providing a monocrystalline substrate; (b) providing at least one layer including a monocrystalline compound semiconductor material; (c) providing at least one intermediate layer separating the substrate and the compound semiconductor material; and (d) arraying the compound semiconductor material to present intervals substantially devoid of the compound semiconductor material that generally establish lateral limits of the predetermined parts.

Abstract translation: 被配置为分成预定部分的半导体层压体具有侧向宽度，并且包括：（a）与侧向宽度大致相邻的单晶基板; （b）至少一层包括单晶化合物半导体材料; 和（c）至少一个基本上分离基板和化合物半导体材料的中间层。 排列至少一个化合物半导体材料层以呈现基本上不含单一化合物半导体材料的间隔，其通常建立预定部分的横向极限。 该方法包括以下步骤：（a）提供单晶衬底; （b）提供包含单晶化合物半导体材料的至少一层; （c）提供分离衬底和化合物半导体材料的至少一个中间层; 和（d）将化合物半导体材料排列成基本上不含通常建立预定部分的横向极限的化合物半导体材料的间隔。

公开(公告)号：US20030020565A1

公开(公告)日：2003-01-30

申请号：US09910799

申请日：2001-07-24

Applicant: MOTOROLA, INC.

Inventor： Kenneth D. Cornett ,  Joseph P. Heck

IPC: H03H009/24

CPC classification number: H03H3/0072

Abstract: Electromechanical resonating devices such as MEMS resonators are provided in semiconductor structures and devices having high-quality monocrystalline semiconductor layers formed by utilizing compliant substrates. The semiconductor layer is patternwise etched to define a vibrational mode resonator member with one or more supports mechanically coupled to the member. A portion beneath the member is etched to provide clearance for vibrational mode operation of the resonating member. The semiconductor layer is selectively doped to define one or more conductive pathways to the resonating member.

Abstract translation: 在通过利用柔性衬底形成的具有高质量单晶半导体层的半导体结构和器件中提供诸如MEMS谐振器的机电谐振装置。 模式蚀刻半导体层以限定具有一个或多个机械耦合到该构件的支撑件的振动模式谐振器构件。 对构件下方的部分进行蚀刻以提供谐振构件的振动模式操作的间隙。 选择性地掺杂半导体层以限定到谐振构件的一个或多个导电路径。