公开(公告)号：US20080203486A1

公开(公告)日：2008-08-28

申请号：US11866491

申请日：2007-10-03

申请人： Maciej Wiatr ,  Frank Wirbeleit ,  Andy Wei ,  Andreas Gehring

发明人： Maciej Wiatr ,  Frank Wirbeleit ,  Andy Wei ,  Andreas Gehring

IPC分类号： H01L27/092 ,  H01L21/04 ,  H01L21/302

CPC分类号： H01L21/823864 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

摘要： By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

摘要翻译： 通过去除用于形成高度复杂的横向掺杂剂分布的晶体管元件的外部间隔物，在形成金属硅化物之前，采用湿化学蚀刻工艺，可以将应力接触衬垫层更靠近 从而允许用于在沟道区域中产生相应应变的高效应力传递机构，而不影响P型区域中的电路元件。

公开(公告)号：US08298924B2

公开(公告)日：2012-10-30

申请号：US11866491

申请日：2007-10-03

申请人： Maciej Wiatr ,  Frank Wirbeleit ,  Andy Wei ,  Andreas Gehring

发明人： Maciej Wiatr ,  Frank Wirbeleit ,  Andy Wei ,  Andreas Gehring

IPC分类号： H01L27/092 ,  H01L21/04

CPC分类号： H01L21/823864 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

摘要： By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

摘要翻译： 通过去除用于形成高度复杂的横向掺杂剂分布的晶体管元件的外部间隔物，在形成金属硅化物之前，采用湿化学蚀刻工艺，可以将应力接触衬垫层更靠近 从而允许用于在沟道区域中产生相应应变的高效应力传递机构，而不影响P型区域中的电路元件。

公开(公告)号：US07939399B2

公开(公告)日：2011-05-10

申请号：US11866461

申请日：2007-10-03

申请人： Anthony Mowry ,  Bernhard Trui ,  Maciej Wiatr ,  Andreas Gehring ,  Andy Wei

发明人： Anthony Mowry ,  Bernhard Trui ,  Maciej Wiatr ,  Andreas Gehring ,  Andy Wei

IPC分类号： H01L21/8238

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78618

摘要： A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the growing material or by other methods such as ion implantation. The highly stress-inducing region near the channel region of a transistor may be covered with an appropriate cover.

摘要翻译： 一种新技术能够提供具有高应力诱导区域的应力诱导合金和可通过适用于商业大容量半导体器件制造环境的标准加工步骤加工的区域。 这些区域可以通过具有变化的生长材料组成的生长过程或通过诸如离子注入的其它方法形成。 在晶体管的沟道区附近的高应力诱导区域可以被适当的覆盖层覆盖。

公开(公告)号：US20080203427A1

公开(公告)日：2008-08-28

申请号：US11866461

申请日：2007-10-03

申请人： Anthony Mowry ,  Bernhard Trui ,  Maciej Wiatr ,  Andreas Gehring ,  Andy Wei

发明人： Anthony Mowry ,  Bernhard Trui ,  Maciej Wiatr ,  Andreas Gehring ,  Andy Wei

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78618

摘要： A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the growing material or by other methods such as ion implantation. The highly stress-inducing region near the channel region of a transistor may be covered with an appropriate cover.

摘要翻译： 一种新技术能够提供具有高应力诱导区域的应力诱导合金和可通过适用于商业大容量半导体器件制造环境的标准加工步骤加工的区域。 这些区域可以通过具有变化的生长材料组成的生长过程或通过诸如离子注入的其它方法形成。 在晶体管的沟道区附近的高应力诱导区域可以被适当的覆盖层覆盖。

公开(公告)号：US07790537B2

公开(公告)日：2010-09-07

申请号：US11937677

申请日：2007-11-09

申请人： Andy Wei ,  Anthony Mowry ,  Andreas Gehring ,  Maciej Wiatr

发明人： Andy Wei ,  Anthony Mowry ,  Andreas Gehring ,  Maciej Wiatr

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7843

摘要： By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.

摘要翻译： 通过在应力记忆技术的基础上引入额外的应变诱导机制，可以显着增加NMOS晶体管的性能，从而减少PMOS晶体管和NMOS晶体管之间的不平衡。 通过在制造过程的不同阶段在掩模层的存在下使各种材料非晶化并再结晶，已经观察到高达约27％的驱动电流改善，具有进一步性能增益的潜力。

公开(公告)号：US20080182371A1

公开(公告)日：2008-07-31

申请号：US11778930

申请日：2007-07-17

申请人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

发明人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC分类号： H01L21/8238

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

摘要： By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

摘要翻译： 通过在高锗浓度的硅/锗材料上提供保护层，相应的应变半导体材料的损失可以显着降低甚至完全避免。 保护层可以在关键的清洁过程之前形成，并且可以保持直到形成金属硅化物区域。 因此，可以在选择性外延生长工艺期间不需要大量过量填充来实现P型晶体管的高性能增益。

公开(公告)号：US20090142900A1

公开(公告)日：2009-06-04

申请号：US12123524

申请日：2008-05-20

申请人： Maciej Wiatr ,  Casey Scott ,  Andreas Gehring ,  Peter Javorka ,  Andy Wei

发明人： Maciej Wiatr ,  Casey Scott ,  Andreas Gehring ,  Peter Javorka ,  Andy Wei

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1079 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7848

摘要： By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.

摘要翻译： 通过选择性地对N沟道晶体管施加应力记忆技术，可以实现晶体管性能的显着改善。 在施加应力记忆方法时的高选择性可以通过在存在可在退火工艺之前不被图案化的适当材料层的情况下退火N沟道晶体管的同时基本上保持P沟道晶体管的结晶状态来实现， 从而避免了额外的光刻和掩蔽步骤。

公开(公告)号：US20080237723A1

公开(公告)日：2008-10-02

申请号：US11937677

申请日：2007-11-09

申请人： Andy Wei ,  Anthony Mowry ,  Andreas Gehring ,  Maciej Wiatr

发明人： Andy Wei ,  Anthony Mowry ,  Andreas Gehring ,  Maciej Wiatr

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7843

摘要： By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.

摘要翻译： 通过在应力记忆技术的基础上引入额外的应变诱导机制，可以显着增加NMOS晶体管的性能，从而减少PMOS晶体管和NMOS晶体管之间的不平衡。 通过在制造过程的不同阶段在掩模层的存在下使各种材料非晶化并再结晶，已经观察到高达约27％的驱动电流改善，具有进一步性能增益的潜力。

公开(公告)号：US08652913B2

公开(公告)日：2014-02-18

申请号：US11778930

申请日：2007-07-17

申请人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

发明人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

摘要： By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

摘要翻译： 通过在高锗浓度的硅/锗材料上提供保护层，相应的应变半导体材料的损失可以显着降低甚至完全避免。 保护层可以在关键的清洁过程之前形成，并且可以保持直到形成金属硅化物区域。 因此，可以在选择性外延生长工艺期间不需要大量过量填充来实现P型晶体管的高性能增益。

公开(公告)号：US07897451B2

公开(公告)日：2011-03-01

申请号：US12123524

申请日：2008-05-20

申请人： Maciej Wiatr ,  Casey Scott ,  Andreas Gehring ,  Peter Javorka ,  Andy Wei

发明人： Maciej Wiatr ,  Casey Scott ,  Andreas Gehring ,  Peter Javorka ,  Andy Wei

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1079 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7848

摘要： By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.

摘要翻译： 通过选择性地对N沟道晶体管施加应力记忆技术，可以实现晶体管性能的显着改善。 在施加应力记忆方法时的高选择性可以通过在存在可在退火工艺之前不被图案化的适当材料层的情况下退火N沟道晶体管的同时基本上保持P沟道晶体管的结晶状态来实现， 从而避免了额外的光刻和掩蔽步骤。