公开(公告)号：US20130200451A1

公开(公告)日：2013-08-08

申请号：US13364948

申请日：2012-02-02

申请人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

摘要翻译： 半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。 在轻掺杂层中形成一个或多个器件。 每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。 每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。 体区与轻掺杂层和重掺杂层具有相反的导电类型。 源区域靠近上表面形成。 在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。 触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

公开(公告)号：US08785278B2

公开(公告)日：2014-07-22

申请号：US13364948

申请日：2012-02-02

申请人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L21/331

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

摘要翻译： 半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。 在轻掺杂层中形成一个或多个器件。 每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。 每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。 体区与轻掺杂层和重掺杂层具有相反的导电类型。 源区域靠近上表面形成。 在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。 触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

公开(公告)号：US20140175536A1

公开(公告)日：2014-06-26

申请号：US13724228

申请日：2012-12-21

申请人： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Liu ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

发明人： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Liu ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L21/033 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/28114 ,  H01L21/3081 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0292 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2 that is larger than the thickness T1 of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度基于沟槽的功率MOSFET。 源触点与第一绝缘间隔件和第二绝缘间隔件自对准，其中第一间隔件耐蚀刻工艺，该蚀刻工艺将选择性地去除由第二间隔件制成的材料。 此外，有源器件可以具有两级栅极氧化物，其中栅极氧化物的下部具有大于栅极氧化物的上部的厚度T1的厚度T2。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08785279B2

公开(公告)日：2014-07-22

申请号：US13561523

申请日：2012-07-30

申请人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

发明人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC分类号： H01L21/336

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 一种形成在半导体衬底中的半导体功率器件，包括在由重掺杂区域支撑的轻掺杂区域的顶部附近的半导体衬底的顶表面附近的高掺杂区域。 所述半导体功率器件还包括向所述高掺杂区域开放的源极沟槽，所述源极沟槽填充有与所述顶部表面附近的所述源极区域电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域相反导电性的掺杂剂的掩埋P区。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20150115333A1

公开(公告)日：2015-04-30

申请号：US14062868

申请日：2013-10-24

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

IPC分类号： H01L29/10 ,  H01L29/808 ,  H01L27/06

CPC分类号： H01L29/1058 ,  H01L27/0727 ,  H01L29/0634 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

摘要翻译： 本发明公开了制造横向功率器件的结构和方法，该器件包括在漏极和栅极之间形成的具有雪崩钳位二极管的超结结构。 横向超结结构降低了导通电阻，而结构增强（包括雪崩钳位二极管和N缓冲区）增加了衬底和漏极之间的击穿电压，并改善了非钳位感应开关（UIS）性能。

公开(公告)号：US20100314682A1

公开(公告)日：2010-12-16

申请号：US12661004

申请日：2010-03-05

申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

公开(公告)号：US09450050B2

公开(公告)日：2016-09-20

申请号：US14062868

申请日：2013-10-24

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingping Guan ,  Yeeheng Lee ,  John Chen

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingping Guan ,  Yeeheng Lee ,  John Chen

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/808 ,  H01L29/06 ,  H01L27/07

CPC分类号： H01L29/1058 ,  H01L27/0727 ,  H01L29/0634 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

摘要翻译： 本发明公开了制造横向功率器件的结构和方法，该器件包括在漏极和栅极之间形成的具有雪崩钳位二极管的超结结构。 横向超结结构降低了导通电阻，而结构增强（包括雪崩钳位二极管和N缓冲区）增加了衬底和漏极之间的击穿电压，并改善了非钳位感应开关（UIS）性能。

公开(公告)号：US08575695B2

公开(公告)日：2013-11-05

申请号：US12592619

申请日：2009-11-30

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

IPC分类号： H01L29/66 ,  H01L21/00

CPC分类号： H01L27/0705 ,  H01L29/0634 ,  H01L29/66901 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

摘要翻译： 本发明公开了制造横向功率器件的结构和方法，该器件包括在漏极和栅极之间形成的具有雪崩钳位二极管的超结结构。 横向超结结构降低了导通电阻，而结构增强（包括雪崩钳位二极管和N缓冲区）增加了衬底和漏极之间的击穿电压，并改善了非钳位感应开关（UIS）性能。

公开(公告)号：US20140027841A1

公开(公告)日：2014-01-30

申请号：US13561523

申请日：2012-07-30

申请人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

发明人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US08390058B2

公开(公告)日：2013-03-05

申请号：US12661004

申请日：2010-03-05

申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。