公开(公告)号：US20080189090A1

公开(公告)日：2008-08-07

申请号：US11671852

申请日：2007-02-06

申请人： Makoto Aikawa ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino ,  Iwao Takiguchi ,  Tetsuji Tamura ,  Yaping Zhou

发明人： Makoto Aikawa ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino ,  Iwao Takiguchi ,  Tetsuji Tamura ,  Yaping Zhou

IPC分类号： G06G7/62 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/318357

摘要： A system and method for determining a guard band for an operating voltage of an integrated circuit device are provided. The system and method provide a mechanism for calculating the guard band based on a comparison of simulated noise obtained from a simulation of the integrated circuit device using a worst case waveform stimuli with simulated or measured power supply noise of a workload/test pattern that may be achieved using testing equipment. A scaling factor for the guard band is determined by comparing results of a simulation of a workload/test pattern with measured results of the workload/test pattern as applied to a hardware implementation of the integrated circuit device. This scaling factor is applied to a difference between the noise generated through simulation of the workload/test pattern and the noise generated through simulation of the worst case current waveform to generate a guard band value.

摘要翻译： 提供了一种用于确定集成电路装置的工作电压的保护带的系统和方法。 该系统和方法提供了一种基于使用最差情况波形刺激从集成电路装置的模拟获得的模拟噪声与可能是工作负载/测试模式的模拟或测量的电源噪声的比较来计算保护频带的机制 使用测试设备实现。 通过将工作负载/测试模式的仿真结果与应用于集成电路设备的硬件实现的工作负载/测试模式的测量结果进行比较来确定保护频带的缩放因子。 该缩放因子被应用于通过模拟工作负载/测试模式产生的噪声与通过模拟最坏情况电流波形产生的噪声之间的差异以产生保护带值。

公开(公告)号：US07486096B2

公开(公告)日：2009-02-03

申请号：US11554712

申请日：2006-10-31

申请人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Charles R. Johns ,  Brad W. Michael ,  Makoto Aikawa ,  Iwao Takiguchi ,  Tetsuji Tamura

发明人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Charles R. Johns ,  Brad W. Michael ,  Makoto Aikawa ,  Iwao Takiguchi ,  Tetsuji Tamura

IPC分类号： G01R31/26

CPC分类号： G01R31/3004

摘要： In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.

摘要翻译： 在一个实施例中，测试系统测试被测器件（DUT）。 DUT包括一个执行内置自检（BIST程序）的内部测试控制器，内置的自检程序包括基于阵列的自动内置自检程序，离散和组合逻辑内置的自检程序 ，和功能体系结构验证程序（AVP），外部制造系统测试控制器管理DUT内的内部测试控制器，并确定提供DUT的电源输入电压的最小工作电压电平。逻辑模拟器提供建模能力 加强DUT的最小电压电源输入运行值的开发。

公开(公告)号：US20080100328A1

公开(公告)日：2008-05-01

申请号：US11554712

申请日：2006-10-31

申请人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Charles R. Johns ,  Brad W. Michael ,  Makoto Aikawa ,  Iwao Takiguchi ,  Tetsuji Tamura

发明人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Charles R. Johns ,  Brad W. Michael ,  Makoto Aikawa ,  Iwao Takiguchi ,  Tetsuji Tamura

IPC分类号： G01R31/26

CPC分类号： G01R31/3004

摘要： In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.

摘要翻译： 在一个实施例中，测试系统测试被测器件（DUT）。 DUT包括一个执行内置自检（BIST程序）的内部测试控制器，内置的自检程序包括基于阵列的自动内置自检程序，离散和组合逻辑内置的自检程序 ，和功能体系结构验证程序（AVP），外部制造系统测试控制器管理DUT内的内部测试控制器，并确定提供DUT的电源输入电压的最小工作电压电平。逻辑模拟器提供建模能力 加强DUT的最小电压电源输入运行值的开发。

公开(公告)号：US07447602B1

公开(公告)日：2008-11-04

申请号：US11758034

申请日：2007-06-05

申请人： Douglas H. Bradley ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino

发明人： Douglas H. Bradley ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino

IPC分类号： G01R21/00 ,  G01R21/06

CPC分类号： G01R31/31721 ,  G01R31/31718

摘要： A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.

摘要翻译： 提供了一种基于热设计点分类处理器芯片的系统和方法。 利用系统和方法，对于每个处理器芯片，在处理器芯片上运行高功率工作负载以确定电压调节器模块（VRM）负载线。 此后，将热设计点（TDP）工作量应用于处理器芯片，并且改变电压直到处理器芯片的性能落在VRM负载线上。 此时，对处理器芯片的电源输入进行测量并用于对处理器芯片进行排序或分页。 应用的各种工作负载具有恒定的频率。 从处理器芯片的这种排序中，可以识别需要较少电压以实现期望频率的低速处理器和在期望频率下运行时消耗较少电流的低电流处理器。

公开(公告)号：US20080092006A1

公开(公告)日：2008-04-17

申请号：US11533432

申请日：2006-09-20

申请人： Nikhil Dakwala ,  Jonathan J. Dement ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael

发明人： Nikhil Dakwala ,  Jonathan J. Dement ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/3187 ,  G01R31/318575

摘要： A method and system for mitigating the impact of voltage supply variations on logic built-in self-test (LBIST) results. The method includes, but is not limited to: creating a set of customized LBIST activation patterns during IC design; propagating the activation patterns from the scan-able latches through the non-scan latches to the device under test; propagating the data from the device under test through the non-scan latches to the scan-able latches; capturing the data in a scan-able latch; and performing each test cycle independently such that the impact of voltage supply variations between test cycles is eliminated.

摘要翻译： 一种用于减轻电压供应变化对逻辑内置自检（LBIST）结果的影响的方法和系统。 该方法包括但不限于：在IC设计期间创建一组定制的LBIST激活模式; 将激活模式从可扫描锁存器通过非扫描锁存器传播到被测器件; 通过非扫描锁存器将数据从被测设备传播到可扫描的锁存器; 在可扫描锁存器中捕获数据; 并且独立地执行每个测试循环，使得消除了测试周期之间的电压供应变化的影响。

公开(公告)号：US20080082887A1

公开(公告)日：2008-04-03

申请号：US11531287

申请日：2006-09-13

申请人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

发明人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318536 ,  G01R31/318575

摘要： A system and method for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

摘要翻译： 提供了一种用于修改测试模式以控制电源噪声的系统和方法。 修改测试图形波形的测试序列中的状态序列的一部分被修改，以便实现近似标称电路电压的电路电压，例如片上电压，例如通过施加其它部分产生的电压 的相同或不同测试序列中的状态序列。 例如，保持状态周期或移位扫描状态周期可以在测试模式波形中的测试状态周期之前被插入或移除。 插入/移除将测试状态周期的发生移动到测试图形波形内，以便调整测试状态周期的电压响应，使得它们更接近于标称电压响应。 以这种方式，可以消除由于电压源中的噪声引起的错误故障。

公开(公告)号：US07610531B2

公开(公告)日：2009-10-27

申请号：US11531287

申请日：2006-09-13

申请人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

发明人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318575

摘要： Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

摘要翻译： 提供了修改测试模式以控制电源噪声的机制。 修改测试图形波形的测试序列中的状态序列的一部分被修改，以便实现近似标称电路电压的电路电压，例如片上电压，例如通过施加其它部分产生的电压 的相同或不同测试序列中的状态序列。 例如，保持状态周期或移位扫描状态周期可以在测试模式波形中的测试状态周期之前被插入或移除。 插入/移除将测试状态周期的发生移动到测试图形波形内，以便调整测试状态周期的电压响应，使得它们更接近于额定电压响应。 以这种方式，可以消除由于电压源中的噪声引起的错误故障。

公开(公告)号：US07203608B1

公开(公告)日：2007-04-10

申请号：US11424613

申请日：2006-06-16

申请人： Makoto Aikawa ,  Sang Hoo Dhong ,  Brian Flachs ,  Paul Marlan Harvey ,  Brad William Michael ,  Yaping Zhou

发明人： Makoto Aikawa ,  Sang Hoo Dhong ,  Brian Flachs ,  Paul Marlan Harvey ,  Brad William Michael ,  Yaping Zhou

IPC分类号： G01R27/28

CPC分类号： G01R27/16 ,  G01R27/205 ,  G01R31/3008

摘要： A method for measuring impedance of a microprocessor chip, electronic packaging, and circuit board power supply system by generating a pseudo-impulse current having a width size in the time domain not larger than the inversion of a maximum frequency of interest and obtaining a voltage measurement in a frequency domain of the pseudo-impulse current. The mechanism of the present invention then predicts the normalized Fourier transformation of the current in the frequency domain, wherein the normalized Fourier transformation depends upon a switching charge of the pseudo-impulse current, measures the switching charge of the pseudo-impulse current, obtains a first current measurement at zero frequency using the measured switching charge, and obtains a second current measurement at a frequency of interest using the first current measurement. The mechanism of the present invention then calculates the impedance of the chip/package/board power supply system using the voltage measurement and the second current measurement.

摘要翻译： 一种用于测量微处理器芯片，电子封装和电路板电源系统的阻抗的方法，其通过产生具有不大于感兴趣的最大频率的反转的时域中的宽度尺寸的伪脉冲电流并获得电压测量 在伪脉冲电流的频域中。 然后，本发明的机构预测频域中的电流的归一化傅里叶变换，其中归一化傅里叶变换取决于伪脉冲电流的切换电荷，测量伪脉冲电流的开关电荷，获得 使用测量的开关电荷在零频率下的第一电流测量，并且使用第一电流测量获得感兴趣频率的第二电流测量。 然后，本发明的机构使用电压测量和第二电流测量来计算芯片/封装/板电源系统的阻抗。

公开(公告)号：US08782381B2

公开(公告)日：2014-07-15

申请号：US13444890

申请日：2012-04-12

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/44

CPC分类号： G06F8/4442 ,  G06F9/3806 ,  G06F12/0875 ,  G06F12/12

摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

摘要翻译： 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。 此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

公开(公告)号：US08627051B2

公开(公告)日：2014-01-07

申请号：US13442919

申请日：2012-04-10

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/44

CPC分类号： G06F9/3806 ,  G06F12/0875

摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

摘要翻译： 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。 此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，这些机制将代码部分的执行重定向到指令高速缓存运行时系统。