公开(公告)号：US08557695B2

公开(公告)日：2013-10-15

申请号：US12974128

申请日：2010-12-21

申请人： Makoto Mizukami ,  Fumitaka Arai

发明人： Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L21/28

CPC分类号： H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储装置，包括：基板; 堆叠部分，其包括多个导体层和交替堆叠在所述基板上的多个绝缘层，所述多个导体层中的至少一层和所述多个绝缘层形成标记层; 电荷累积膜，其形成在从其顶表面到底表面形成在堆叠部分中的存储器插塞孔的内表面上; 以及通过电荷累积膜形成在存储器插塞孔内部的半导体柱。

公开(公告)号：US07804133B2

公开(公告)日：2010-09-28

申请号：US12022382

申请日：2008-01-30

申请人： Takeshi Murata ,  Makoto Mizukami ,  Fumitaka Arai

发明人： Takeshi Murata ,  Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L27/115

CPC分类号： H01L27/105 ,  H01L21/84 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/1203

摘要： Semiconductor storage devices in which a plurality of semiconductor element devices having different functions are disposed in the appropriate region of the partial SOI substrate and the interface between each gate insulator and each gate electrode is formed to be the same level, and manufacturing methods thereof are disclosed. According to one aspect, there is provided a semiconductor storage device includes a first semiconductor region provided in a semiconductor substrate including a buried insulator having opening portions, a second semiconductor region without including buried insulator, a plurality of first semiconductor element devices disposed above the buried insulator, a plurality of second semiconductor element devices each disposed in a region including a region above the opening portion of the buried insulator, and a plurality of third semiconductor element devices disposed in the second semiconductor region.

摘要翻译： 其中具有不同功能的多个半导体元件器件设置在部分SOI衬底的适当区域中并且每个栅绝缘体和每个栅电极之间的界面形成为相同水平的半导体存储器件，并且其制造方法被公开 。 根据一个方面，提供一种半导体存储装置，包括设置在包括具有开口部分的埋入式绝缘体的半导体衬底中的第一半导体区域，不包括埋入绝缘体的第二半导体区域，设置在掩埋层上方的多个第一半导体元件器件 绝缘体，多个第二半导体元件器件，每个第二半导体元件器件设置在包括所述埋入绝缘体的开口部分上方的区域的区域中，以及设置在所述第二半导体区域中的多个第三半导体元件器件。

公开(公告)号：US07696559B2

公开(公告)日：2010-04-13

申请号：US11616522

申请日：2006-12-27

申请人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

发明人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

IPC分类号： H01L27/115

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

摘要翻译： 半导体存储器件包括：在单元阵列区域中形成有杂质扩散层的半导体衬底; 形成在电池阵列区域上的栅极布线堆叠体，其中多个栅极布线彼此堆叠并且用绝缘膜分离; 形成在栅极布线堆叠体的侧表面上的栅极绝缘膜，其中包含绝缘电荷存储层，沿着栅极布线堆叠体布置的柱状半导体层，其一个侧表面与栅极布线相对 堆叠体经由栅极绝缘膜，每个柱状半导体层具有与杂质扩散层相同的导电类型; 以及形成为与柱状半导体层的上表面接触并与栅极布线相交的数据线。

公开(公告)号：US20110024827A1

公开(公告)日：2011-02-03

申请号：US12904231

申请日：2010-10-14

申请人： Fumitaka ARAI ,  Ichiro Mizushima ,  Makoto Mizukami

发明人： Fumitaka ARAI ,  Ichiro Mizushima ,  Makoto Mizukami

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42348 ,  H01L29/792

摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括：在其表面具有SOI区域和外延区域的半导体衬底，设置在SOI区域中的半导体衬底上的掩埋氧化膜，布置在掩埋氧化物上的SOI层 膜，布置在SOI层上的多个存储单元，布置在外延区中的外延层和布置在外延层上的选择栅极晶体管，其中SOI层由微晶层制成。

公开(公告)号：US20100159657A1

公开(公告)日：2010-06-24

申请号：US12715964

申请日：2010-03-02

申请人： Fumitaka ARAI ,  Riichiro Shirota ,  Makoto Mizukami

发明人： Fumitaka ARAI ,  Riichiro Shirota ,  Makoto Mizukami

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

摘要翻译： 半导体存储器件包括：在单元阵列区域中形成有杂质扩散层的半导体衬底; 形成在电池阵列区域上的栅极布线堆叠体，其中多个栅极布线彼此堆叠并且用绝缘膜分离; 形成在栅极布线堆叠体的侧表面上的栅极绝缘膜，其中包含绝缘电荷存储层; 沿着栅极布线堆叠体排列的柱状半导体层，其一个侧表面经由栅极绝缘膜与栅极布线堆叠体相对，每个柱状半导体层具有与杂质扩散层相同的导电类型; 以及形成为与柱状半导体层的上表面接触并与栅极布线相交的数据线。

公开(公告)号：US20080073695A1

公开(公告)日：2008-03-27

申请号：US11841257

申请日：2007-08-20

申请人： Makoto Mizukami ,  Riichiro Shirota ,  Fumitaka Arai

发明人： Makoto Mizukami ,  Riichiro Shirota ,  Fumitaka Arai

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/11524 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203

摘要： A semiconductor memory including a plurality of cell units arranged in a row direction, each of the cell units includes: a semiconductor region; a first buried insulating film provided on the semiconductor region; a second buried insulating film provided on the first buried insulating film, which has higher dielectric constant than the first buried insulating film; a semiconductor layer provided on the second buried insulating film; and a plurality of memory cell transistors arranged in a column direction, each of the memory cell transistors having a source region, a drain region and a channel region defined in the semiconductor layer.

摘要翻译： 一种半导体存储器，包括沿行方向布置的多个单元单元，每个单元单元包括：半导体区域; 设置在半导体区域上的第一掩埋绝缘膜; 设置在第一掩埋绝缘膜上的第二掩埋绝缘膜，其具有比第一掩埋绝缘膜更高的介电常数; 设置在所述第二掩埋绝缘膜上的半导体层; 以及沿列方向布置的多个存储单元晶体管，每个存储单元晶体管具有限定在半导体层中的源极区，漏极区和沟道区。

公开(公告)号：US07829948B2

公开(公告)日：2010-11-09

申请号：US11963046

申请日：2007-12-21

申请人： Fumitaka Arai ,  Ichiro Mizushima ,  Makoto Mizukami

发明人： Fumitaka Arai ,  Ichiro Mizushima ,  Makoto Mizukami

IPC分类号： H01L27/11

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42348 ,  H01L29/792

摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括：在其表面具有SOI区域和外延区域的半导体衬底，设置在SOI区域中的半导体衬底上的掩埋氧化膜，布置在掩埋氧化物上的SOI层 膜，布置在SOI层上的多个存储单元，布置在外延区中的外延层和布置在外延层上的选择栅极晶体管，其中SOI层由微晶层制成。

公开(公告)号：US07553728B2

公开(公告)日：2009-06-30

申请号：US12206762

申请日：2008-09-09

申请人： Makoto Mizukami ,  Fumitaka Arai

发明人： Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L21/336 ,  H01L27/108

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

摘要翻译： 具有多个存储单元晶体管的线性排列的非易失性半导体存储器包括：具有第一导电类型的第一半导体层; 第二半导体层，设置在所述第一半导体层上以防止杂质从所述第一半导体层扩散到所述第二半导体层上方的区域; 以及设置在所述第二半导体层上的第三半导体层，包括具有第二导电类型的第一源极区域，具有第二导电类型的第一漏极区域和具有用于每个存储单元晶体管的第二导电类型的第一沟道区域。

公开(公告)号：US20080157092A1

公开(公告)日：2008-07-03

申请号：US11963046

申请日：2007-12-21

申请人： Fumitaka Arai ,  Ichiro Mizushima ,  Makoto Mizukami

发明人： Fumitaka Arai ,  Ichiro Mizushima ,  Makoto Mizukami

IPC分类号： H01L27/11

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42348 ,  H01L29/792

摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括：在其表面具有SOI区域和外延区域的半导体衬底，设置在SOI区域中的半导体衬底上的掩埋氧化膜，布置在掩埋氧化物上的SOI层 膜，布置在SOI层上的多个存储单元，布置在外延区中的外延层和布置在外延层上的选择栅极晶体管，其中SOI层由微晶层制成。

公开(公告)号：US20070158736A1

公开(公告)日：2007-07-12

申请号：US11616522

申请日：2006-12-27

申请人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

发明人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

摘要翻译： 半导体存储器件包括：在单元阵列区域中形成有杂质扩散层的半导体衬底; 形成在电池阵列区域上的栅极布线堆叠体，其中多个栅极布线彼此堆叠并且用绝缘膜分离; 形成在栅极布线堆叠体的侧表面上的栅极绝缘膜，其中包含绝缘电荷存储层，沿着栅极布线堆叠体布置的柱状半导体层，其一个侧表面与栅极布线相对 堆叠体经由栅极绝缘膜，每个柱状半导体层具有与杂质扩散层相同的导电类型; 以及形成为与柱状半导体层的上表面接触并与栅极布线相交的数据线。