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1.发明授权公开(公告)号：US06329680B1
公开(公告)日：2001-12-11
申请号：US09479592
申请日：2000-01-07
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L21/76895 , H01L23/485 , H01L23/53223 , H01L27/10873 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.
摘要翻译： 到达n +型半导体区域的多个第一接触孔用作逻辑DRAM混合物LSI中使用的MISFET的源极和到达用作MISFET的漏极的另一n +型半导体区域的多个第二接触孔， 穿过在MISFET的栅电极上形成的绝缘层。 与位线相同的层上的导电膜通过第一接触孔分流用作源的n +型半导体区域。 另一导电膜通过第二接触孔分流用作漏极的n +型半导体区域。
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2.发明授权公开(公告)号：US06420227B1
公开(公告)日：2002-07-16
申请号：US09518146
申请日：2000-03-03
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/76895 , H01L23/485 , H01L23/53223 , H01L27/10873 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.
摘要翻译： 到达n +型半导体区域的多个第一接触孔用作逻辑DRAM混合物LSI中使用的MISFET的源极和到达用作MISFET的漏极的另一n +型半导体区域的多个第二接触孔， 穿过在MISFET的栅电极上形成的绝缘层。 与位线相同的层上的导电膜通过第一接触孔分流用作源的n +型半导体区域。 另一导电膜通过第二接触孔分流用作漏极的n +型半导体区域。
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公开(公告)号：US06501115B2
公开(公告)日：2002-12-31
申请号：US09988586
申请日：2001-11-20
IPC分类号： H01L2976
CPC分类号： H01L27/10894 , H01L21/76895 , H01L23/485 , H01L23/53223 , H01L27/10873 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.
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4.发明授权Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method 失效半导体集成电路器件的制造方法以及由其制造的半导体集成电路器件公开(公告)号：US07109076B2
公开(公告)日：2006-09-19
申请号：US10855402
申请日：2004-05-28
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10814 , H01L27/10897 , H01L27/11 , H01L27/1104 , H01L27/1116
摘要： Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.
摘要翻译： 在n沟道型MISFET和p型沟道型MISFET之间的边界附近，抑制了栅电极中的杂质的相互扩散，其采用多选择性双栅结构。 由于n沟道型MISFET的栅电极和p沟道型MISFET的栅电极具有相互不同的导电类型，它们被分离以防止杂质的相互扩散，并且通过金属 布线按以下步骤形成。 在将栅电极材料图案化以分离栅电极之前的步骤中，通过在700℃以上的温度下不进行热处理来防止在形成栅电极之前杂质的相互扩散。
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公开(公告)号：US20050026358A1
公开(公告)日：2005-02-03
申请号：US10930845
申请日：2004-09-01
申请人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
发明人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
IPC分类号： H01L21/02 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108
CPC分类号： H01L27/10885 , H01L21/02164 , H01L21/02274 , H01L21/02318 , H01L21/31604 , H01L21/31612 , H01L21/32051 , H01L21/76801 , H01L21/76828 , H01L21/76832 , H01L21/76837 , H01L27/10814 , H01L28/84 , H01L28/90
摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, a high density plasma silicon oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor, to be connected to the other of the source and drain region of the memory cell selection MISFET, is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.
摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，通过高密度等离子体CVD技术将高密度等离子体氧化硅膜沉积在与DRAM存储单元的存储单元选择MISFET的源极和漏极区连接的位线上， 结构在750℃下进行RTA（热处理）。抛光表面，然后形成要连接到存储单元选择MISFET的源极和漏极区域中的另一个的电容器。 结果，即使当用作电容器的电容绝缘膜的氧化钽膜进行热处理时，施加在位线上的膜应力减小，位线的断裂和分离是 防止了
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公开(公告)号：US20060275969A1
公开(公告)日：2006-12-07
申请号：US11503161
申请日：2006-08-14
IPC分类号： H01L21/8234
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10814 , H01L27/10897 , H01L27/11 , H01L27/1104 , H01L27/1116
摘要： Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.
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公开(公告)号：US07084055B2
公开(公告)日：2006-08-01
申请号：US10930845
申请日：2004-09-01
申请人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
发明人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
IPC分类号： H01L21/4763
CPC分类号： H01L27/10885 , H01L21/02164 , H01L21/02274 , H01L21/02318 , H01L21/31604 , H01L21/31612 , H01L21/32051 , H01L21/76801 , H01L21/76828 , H01L21/76832 , H01L21/76837 , H01L27/10814 , H01L28/84 , H01L28/90
摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes. In heat treating the high density plasma silicon oxide film, the temperature is raised from the first temperature to the second temperature at a maximum speed of 60° C./second or less.
摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，公开了一种方法，其中例如将高密度等离子体氧化硅膜沉积在布线（例如，连接到DRAM存储器的存储器单元选择MISFET的源极和漏极区域的位线） 在第一温度下，通过高密度等离子体CVD技术，在高于第一温度（例如750℃）的第二温度下对该结构进行RTA（热处理）。 然后在高密度等离子体氧化硅膜中形成通孔，然后形成第一和第二导电膜，第一导电膜形成在通孔中并且在比第一温度低的第三温度下形成。 然后抛光第一和第二导电层以选择性地保持在通孔内。 在高密度等离子体氧化硅膜的热处理中，以60℃/秒以下的最高速度将温度从第一温度升高到第二温度。
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公开(公告)号：US06803271B2
公开(公告)日：2004-10-12
申请号：US10187003
申请日：2002-07-02
申请人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
发明人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L21/02164 , H01L21/02274 , H01L21/02318 , H01L21/31604 , H01L21/31612 , H01L21/32051 , H01L21/76801 , H01L21/76828 , H01L21/76832 , H01L21/76837 , H01L27/10814 , H01L28/84 , H01L28/90
摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.
摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，HDP硅氧化物膜通过高密度等离子体CVD技术沉积在与DRAM存储单元的存储单元选择MISFET的源极和漏极区域连接的位线上，结构是 在750℃下进行RTA（热处理）。抛光表面，然后形成要连接到存储单元选择MISFET的源极和漏极区域中的另一个的电容器。 结果，即使当用作电容器的电容绝缘膜的氧化钽膜进行热处理时，施加在位线上的膜应力减小，位线的断裂和分离是 防止了
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