公开(公告)号：US20050026358A1

公开(公告)日：2005-02-03

申请号：US10930845

申请日：2004-09-01

申请人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

发明人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

CPC分类号： H01L27/10885 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90

摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, a high density plasma silicon oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor, to be connected to the other of the source and drain region of the memory cell selection MISFET, is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，通过高密度等离子体CVD技术将高密度等离子体氧化硅膜沉积在与DRAM存储单元的存储单元选择MISFET的源极和漏极区连接的位线上， 结构在750℃下进行RTA（热处理）。抛光表面，然后形成要连接到存储单元选择MISFET的源极和漏极区域中的另一个的电容器。 结果，即使当用作电容器的电容绝缘膜的氧化钽膜进行热处理时，施加在位线上的膜应力减小，位线的断裂和分离是 防止了

公开(公告)号：US07084055B2

公开(公告)日：2006-08-01

申请号：US10930845

申请日：2004-09-01

申请人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

发明人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

IPC分类号： H01L21/4763

CPC分类号： H01L27/10885 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90

摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes. In heat treating the high density plasma silicon oxide film, the temperature is raised from the first temperature to the second temperature at a maximum speed of 60° C./second or less.

摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，公开了一种方法，其中例如将高密度等离子体氧化硅膜沉积在布线（例如，连接到DRAM存储器的存储器单元选择MISFET的源极和漏极区域的位线） 在第一温度下，通过高密度等离子体CVD技术，在高于第一温度（例如750℃）的第二温度下对该结构进行RTA（热处理）。 然后在高密度等离子体氧化硅膜中形成通孔，然后形成第一和第二导电膜，第一导电膜形成在通孔中并且在比第一温度低的第三温度下形成。 然后抛光第一和第二导电层以选择性地保持在通孔内。 在高密度等离子体氧化硅膜的热处理中，以60℃/秒以下的最高速度将温度从第一温度升高到第二温度。

公开(公告)号：US06803271B2

公开(公告)日：2004-10-12

申请号：US10187003

申请日：2002-07-02

申请人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

发明人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90

摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，HDP硅氧化物膜通过高密度等离子体CVD技术沉积在与DRAM存储单元的存储单元选择MISFET的源极和漏极区域连接的位线上，结构是 在750℃下进行RTA（热处理）。抛光表面，然后形成要连接到存储单元选择MISFET的源极和漏极区域中的另一个的电容器。 结果，即使当用作电容器的电容绝缘膜的氧化钽膜进行热处理时，施加在位线上的膜应力减小，位线的断裂和分离是 防止了

公开(公告)号：US07078815B2

公开(公告)日：2006-07-18

申请号：US11056224

申请日：2005-02-14

申请人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

发明人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.

摘要翻译： 半导体集成电路器件具有半导体衬底，包括形成在半导体衬底的主表面上的SiOF膜的层间绝缘膜，通过层间绝缘膜的干蚀刻形成的布线槽和通过布线槽埋入布线槽中的Cu布线 一种镶嵌法，其中在用作干蚀刻的蚀刻停止层的氮化硅膜和SiOF膜之间提供氧氮化硅膜，使得在SiOF膜中产生的游离F被氧氮化硅膜捕获。

公开(公告)号：US07282434B2

公开(公告)日：2007-10-16

申请号：US11485976

申请日：2006-07-14

申请人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

发明人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

摘要翻译： 提供一种制造半导体集成电路器件的方法，包括在半导体衬底的主表面上形成由含氟氧化硅构成的第一绝缘膜，同时形成包含氧化硅作为主要成分的第二绝缘膜，形成 以碳化硅为主要成分的第三绝缘膜，形成由含氟氧化硅构成的第四绝缘膜。 通过使用第一光致抗蚀剂膜作为掩模的干蚀刻在其布线槽形成区域处去除第四绝缘膜。 第一导电层被埋在布线槽内部，并且通过化学机械抛光方法从布线槽的外部去除第一导电层，从而在布线槽内形成包括第一导电层的第一布线。

公开(公告)号：US20050151262A1

公开(公告)日：2005-07-14

申请号：US11056224

申请日：2005-02-14

申请人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

发明人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

IPC分类号： H01L23/522 ,  H01L21/304 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.

公开(公告)号：US06856019B2

公开(公告)日：2005-02-15

申请号：US10214579

申请日：2002-08-09

申请人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

发明人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

IPC分类号： H01L23/522 ,  H01L21/304 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.

摘要翻译： 半导体集成电路器件具有半导体衬底，包括形成在半导体衬底的主表面上的SiOF膜的层间绝缘膜，通过层间绝缘膜的干蚀刻形成的布线槽和通过布线槽埋入布线槽中的Cu布线 一种镶嵌法，其中在用作干蚀刻的蚀刻停止层的氮化硅膜和SiOF膜之间提供氧氮化硅膜，使得在SiOF膜中产生的游离F被氧氮化硅膜捕获。

公开(公告)号：US20060258149A1

公开(公告)日：2006-11-16

申请号：US11485976

申请日：2006-07-14

申请人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

发明人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

摘要翻译： 提供一种制造半导体集成电路器件的方法，包括在半导体衬底的主表面上形成由含氟氧化硅构成的第一绝缘膜，同时形成包含氧化硅作为主要成分的第二绝缘膜，形成 以碳化硅为主要成分的第三绝缘膜，形成由含氟氧化硅构成的第四绝缘膜。 通过使用第一光致抗蚀剂膜作为掩模的干蚀刻在其布线槽形成区域处除去第四绝缘膜。 第一导电层被埋在布线槽内部，并且通过化学机械抛光方法从布线槽的外部去除第一导电层，从而在布线槽内形成包括第一导电层的第一布线。