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    Semiconductor integrated circuit device and process for manufacture of the same
    1.
    发明授权
    Semiconductor integrated circuit device and process for manufacture of the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06420227B1

    公开(公告)日：2002-07-16

    申请号：US09518146

    申请日：2000-03-03

    申请人： Makoto Yoshida ,  Katsuyuki Asaka ,  Toshihiko Takakura

    发明人： Makoto Yoshida ,  Katsuyuki Asaka ,  Toshihiko Takakura

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53223 ,  H01L27/10873 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.

    摘要翻译： 到达n +型半导体区域的多个第一接触孔用作逻辑DRAM混合物LSI中使用的MISFET的源极和到达用作MISFET的漏极的另一n +型半导体区域的多个第二接触孔， 穿过在MISFET的栅电极上形成的绝缘层。 与位线相同的层上的导电膜通过第一接触孔分流用作源的n +型半导体区域。 另一导电膜通过第二接触孔分流用作漏极的n +型半导体区域。

    Semiconductor integrated circuit device and process for manufacturing the same
    2.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06329680B1

    公开(公告)日：2001-12-11

    申请号：US09479592

    申请日：2000-01-07

    申请人： Makoto Yoshida ,  Katsuyuki Asaka ,  Toshihiko Takakura

    发明人： Makoto Yoshida ,  Katsuyuki Asaka ,  Toshihiko Takakura

    IPC分类号： H01L27108

    CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53223 ,  H01L27/10873 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.

    摘要翻译： 到达n +型半导体区域的多个第一接触孔用作逻辑DRAM混合物LSI中使用的MISFET的源极和到达用作MISFET的漏极的另一n +型半导体区域的多个第二接触孔， 穿过在MISFET的栅电极上形成的绝缘层。 与位线相同的层上的导电膜通过第一接触孔分流用作源的n +型半导体区域。 另一导电膜通过第二接触孔分流用作漏极的n +型半导体区域。

    Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill
    6.
    发明授权
    Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill 失效
    用于制造具有厚氧化膜和凹槽蚀刻和再填充的半导体集成电路器件的方法

    公开(公告)号：US4853343A

    公开(公告)日：1989-08-01

    申请号：US169748

    申请日：1988-03-18

    申请人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

    发明人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

    IPC分类号： H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/73

    CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/76202 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S438/981

    摘要： A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

    摘要翻译： 公开了一种采用新的隔离工艺的半导体器件，其中隔离区域是通过各向异性干法蚀刻将掩埋材料埋入形成在半导体主体中的宽度基本恒定的深沟槽的区域，半导体元件形成为选定的 通过隔离区域隔离的半导体区域以及其中没有形成半导体元件的其它半导体区域，其全部表面被由半导体本体的局部氧化产生的厚氧化膜覆盖。 新的隔离工艺非常适用于双极型半导体器件，其中深沟形成为通过N +型掩埋层到达半导体衬底，并且与上述厚氧化膜隔离物同时形成的厚氧化膜 双极晶体管的基极区域和集电极接触区域。

    Isolation regions formed by locos followed with groove etch and refill
    7.
    发明授权
    Isolation regions formed by locos followed with groove etch and refill 失效
    由区域形成的隔离区域随后进行凹槽蚀刻和再填充

    公开(公告)号：US4746963A

    公开(公告)日：1988-05-24

    申请号：US946778

    申请日：1986-12-29

    申请人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

    发明人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

    IPC分类号： H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/73 ,  H01L21/95

    CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/76202 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S438/981

    摘要： A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

    摘要翻译： 公开了一种采用新的隔离工艺的半导体器件，其中隔离区域是通过各向异性干法蚀刻将掩埋材料埋入形成在半导体主体中的宽度基本恒定的深沟槽的区域，半导体元件形成为选定的 通过隔离区域隔离的半导体区域以及其中没有形成半导体元件的其它半导体区域，其全部表面被由半导体本体的局部氧化产生的厚氧化膜覆盖。 新的隔离工艺非常适用于双极型半导体器件，其中深沟形成为通过N +型掩埋层到达半导体衬底，并且与上述厚氧化膜隔离物同时形成的厚氧化膜 双极晶体管的基极区域和集电极接触区域。

    Method of forming trench isolation in an integrated circuit
    8.
    发明授权
    Method of forming trench isolation in an integrated circuit 失效
    在集成电路中形成沟槽隔离的方法

    公开(公告)号：US4700464A

    公开(公告)日：1987-10-20

    申请号：US661116

    申请日：1984-10-15

    申请人： Daisuke Okada ,  Akihisa Uchida ,  Toshihiko Takakura ,  Shinji Nakashima ,  Nobuhiko Ohno ,  Katsumi Ogiue

    发明人： Daisuke Okada ,  Akihisa Uchida ,  Toshihiko Takakura ,  Shinji Nakashima ,  Nobuhiko Ohno ,  Katsumi Ogiue

    IPC分类号： H01L21/31 ,  H01L21/331 ,  H01L21/76 ,  H01L21/763 ,  H01L29/73 ,  H01L29/732 ,  H01L21/22 ,  H01L21/302

    CPC分类号： H01L21/763 ,  H01L21/76 ,  Y10S438/978

    摘要： A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

    摘要翻译： 在半导体集成电路器件中设有在半导体衬底中蚀刻的多晶硅填充U形沟槽，以形成防止多晶硅与形成在半导体衬底上的电极之间的任何短路的隔离区域。 在U形槽内形成二氧化硅膜，在其上进一步形成氮化硅膜和二氧化硅膜。 氮化硅膜具有高硬度，其抑制了当多晶硅氧化时多晶硅的表面膨胀导致外围活性区域的晶体缺陷的发展。 当多晶硅的表面被氧化时，氧化膜沿着氮化物膜的氧化膜进行氧化，使得整个氧化膜形成得较厚。 因此，氮化硅膜和二氧化硅膜相对于用于形成接触孔的蚀刻具有增加的裕度。

    Liquid crystal shutter and printhead
    9.
    发明授权
    Liquid crystal shutter and printhead 有权
    液晶快门和打印头

    公开(公告)号：US07170569B2

    公开(公告)日：2007-01-30

    申请号：US10787069

    申请日：2004-02-24

    申请人： Toshihiko Takakura

    发明人： Toshihiko Takakura

    IPC分类号： G02F1/13

    CPC分类号： G02F1/133512 ,  G02F1/133345 ,  G02F2001/133357 ,  G02F2203/12

    摘要： The present invention relates to a liquid crystal shutter (5). The liquid crystal shutter (5) includes a first and a second transparent substrates (50), (51) arranged to face each other; a light shielding film (52) formed on a surface (511) of the second transparent substrate (51), which faces the first transparent substrate (50), for restricting incidence of light travelling from the first transparent substrate (50) to the second transparent substrate (51); and transparent electrodes (54b) laminated over the light shielding film (52). The transparent electrodes (54b) are laminated over the light shielding film (52) via a single insulating layer (53b). Each of the transparent electrodes (54b), the light shielding film (52) and the insulating layer (53b) is made of an inorganic substance.

    摘要翻译： 本发明涉及液晶快门（5）。 液晶快门（5）包括彼此相对配置的第一和第二透明基板（50），（51） 形成在与第一透明基板（50）相对的第二透明基板（51）的表面（511）上的遮光膜（52），用于限制从第一透明基板（50）向第二透明基板 透明基板（51）。 以及层叠在遮光膜（52）上的透明电极（54b）。 透明电极（54b）通过单个绝缘层（53b）层压在遮光膜（52）上。 透明电极（54b），遮光膜（52）和绝缘层（53b）分别由无机物质构成。

    Image sensor unit and image scanner incorporating the same
    10.
    发明授权
    Image sensor unit and image scanner incorporating the same 失效
    图像传感器单元和包含其的图像扫描仪

    公开(公告)号：US06339214B1

    公开(公告)日：2002-01-15

    申请号：US09369703

    申请日：1999-08-06

    申请人： Toshihiko Takakura ,  Hisayoshi Fujimoto

    发明人： Toshihiko Takakura ,  Hisayoshi Fujimoto

    IPC分类号： H04N124

    CPC分类号： H04N1/0303 ,  H04N1/03 ,  H04N1/0305

    摘要： An image sensor unit for reading documents includes a casing elongated in the primary scanning direction, a light source, at least a pair of mirrors held in facing relation for alternately reflecting light, a lens unit for focusing light reflected on the document, and a sensor for receiving the light focused by the lens unit. For reducing the vertical dimension of the image sensor unit, the paired mirrors are spaced from each other in the secondary scanning direction within the casing.

    摘要翻译： 用于读取原稿的图像传感器单元包括：在主扫描方向上伸长的外壳，光源，至少一对保持在面对中的交替反射光的反射镜;用于聚​​焦在文档上反射的光的透镜单元;以及传感器 用于接收由镜头单元聚焦的光。 为了减小图像传感器单元的垂直尺寸，成对的反射镜在壳体内沿副扫描方向彼此间隔开。