公开(公告)号：US07084055B2

公开(公告)日：2006-08-01

申请号：US10930845

申请日：2004-09-01

申请人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

发明人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

IPC分类号： H01L21/4763

CPC分类号： H01L27/10885 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90

摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes. In heat treating the high density plasma silicon oxide film, the temperature is raised from the first temperature to the second temperature at a maximum speed of 60° C./second or less.

摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，公开了一种方法，其中例如将高密度等离子体氧化硅膜沉积在布线（例如，连接到DRAM存储器的存储器单元选择MISFET的源极和漏极区域的位线） 在第一温度下，通过高密度等离子体CVD技术，在高于第一温度（例如750℃）的第二温度下对该结构进行RTA（热处理）。 然后在高密度等离子体氧化硅膜中形成通孔，然后形成第一和第二导电膜，第一导电膜形成在通孔中并且在比第一温度低的第三温度下形成。 然后抛光第一和第二导电层以选择性地保持在通孔内。 在高密度等离子体氧化硅膜的热处理中，以60℃/秒以下的最高速度将温度从第一温度升高到第二温度。

公开(公告)号：US06803271B2

公开(公告)日：2004-10-12

申请号：US10187003

申请日：2002-07-02

申请人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

发明人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90

摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，HDP硅氧化物膜通过高密度等离子体CVD技术沉积在与DRAM存储单元的存储单元选择MISFET的源极和漏极区域连接的位线上，结构是 在750℃下进行RTA（热处理）。抛光表面，然后形成要连接到存储单元选择MISFET的源极和漏极区域中的另一个的电容器。 结果，即使当用作电容器的电容绝缘膜的氧化钽膜进行热处理时，施加在位线上的膜应力减小，位线的断裂和分离是 防止了

公开(公告)号：US20050026358A1

公开(公告)日：2005-02-03

申请号：US10930845

申请日：2004-09-01

申请人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

发明人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

CPC分类号： H01L27/10885 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90

摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, a high density plasma silicon oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor, to be connected to the other of the source and drain region of the memory cell selection MISFET, is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，通过高密度等离子体CVD技术将高密度等离子体氧化硅膜沉积在与DRAM存储单元的存储单元选择MISFET的源极和漏极区连接的位线上， 结构在750℃下进行RTA（热处理）。抛光表面，然后形成要连接到存储单元选择MISFET的源极和漏极区域中的另一个的电容器。 结果，即使当用作电容器的电容绝缘膜的氧化钽膜进行热处理时，施加在位线上的膜应力减小，位线的断裂和分离是 防止了

公开(公告)号：US08551857B2

公开(公告)日：2013-10-08

申请号：US13034749

申请日：2011-02-25

申请人： Yuji Imamura ,  Tsuyoshi Fujiwara ,  Toyohiko Kuno

发明人： Yuji Imamura ,  Tsuyoshi Fujiwara ,  Toyohiko Kuno

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L23/53238 ,  H01L27/0688 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.

摘要翻译： 提供了通过少量步骤制造高电容和高精度MIM静电电容器的技术。 在第一层间绝缘膜上同时形成静电电容器和第二布线的下电极之后，在沉积在第一层间绝缘膜上的第二层间绝缘膜中形成开口部。 接下来，在包括开口部的内部的第二层间绝缘膜上顺序地沉积电容绝缘膜，第二金属膜和保护金属膜，并且在保护金属膜，第二金属膜和电容绝缘膜上 通过CMP法对第二层间绝缘膜进行抛光和去除，从而使电容绝缘膜，由第二金属膜制成的上电极和保护金属膜保持在开口部分。

公开(公告)号：US07762021B2

公开(公告)日：2010-07-27

申请号：US10554832

申请日：2004-10-19

申请人： Tsuyoshi Fujiwara ,  Yoshihiro Manabe ,  Taishi Ogawa ,  Yoshiaki Meguro

发明人： Tsuyoshi Fujiwara ,  Yoshihiro Manabe ,  Taishi Ogawa ,  Yoshiaki Meguro

IPC分类号： B60J5/04

CPC分类号： B60J5/0402 ,  B60R13/04 ,  Y10T29/49622 ,  Y10T29/49915 ,  Y10T428/12354

摘要： A vehicular door sash includes a sash frame formed by subjecting a predetermined metal sheet to a roll molding process to have a predetermined cross section. The sash frame includes a groove portion for retaining a glass-run channel, a retainer portion for retaining a weather strip, a flange portion that connects the retainer portion and the groove portion and partially forms an outer surface of a door of a vehicle, and a sash molding configured to cover the flange portion. The flange portion has a first configuration in which the flange portion is not covered by the sash molding and a second configuration in which the flange portion is covered and compressed by the sash molding.

摘要翻译： 车门框包括通过对预定的金属板进行辊模制成而具有预定横截面而形成的窗框。 窗框包括用于保持玻璃通道的槽部分，用于保持耐候条的保持器部分，连接保持器部分和槽部分并部分地形成车辆门的外表面的凸缘部分，以及 构造成覆盖凸缘部分的窗框模制件。 凸缘部具有第一构造，其中凸缘部分不被窗框模制件覆盖，并且凸缘部分被窗框模制件覆盖和压缩的第二构造。

公开(公告)号：US20060289917A1

公开(公告)日：2006-12-28

申请号：US11473229

申请日：2006-06-23

申请人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Takeshi Saikawa ,  Yoshihiro Kawasaki ,  Mitsuhiro Toya ,  Shunji Mori ,  Yoshiyuki Okabe

发明人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Takeshi Saikawa ,  Yoshihiro Kawasaki ,  Mitsuhiro Toya ,  Shunji Mori ,  Yoshiyuki Okabe

IPC分类号： H01L29/94

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/87

摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

摘要翻译： 提供了一种能够减小电容器的寄生电容同时减小电容器所占空间的技术。 通过在由下电极构成的电容器，电容绝缘膜和中间电极上形成电容器，由中间电极，另一电容绝缘膜和上电极构成的另一电容器形成堆叠结构。 由于中间电极具有台阶差，所以在电容器形成区域以外的区域中，中间电极和下部电极之间的距离以及中间电极和上部电极之间的距离变得比电容器形成区域的大。 例如，下电极与电容器形成区域中的电容绝缘膜直接接触，而在电容器形成区域以外的区域中，下电极不与电容器绝缘膜直接接触。

公开(公告)号：US06746913B2

公开(公告)日：2004-06-08

申请号：US10083416

申请日：2002-02-27

申请人： Tsuyoshi Fujiwara ,  Takeshi Saikawa ,  Ryouichi Furukawa ,  Masato Kunitomo

发明人： Tsuyoshi Fujiwara ,  Takeshi Saikawa ,  Ryouichi Furukawa ,  Masato Kunitomo

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31612 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894

摘要： A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.

摘要翻译： 在其上形成有半导体集成电路器件的电容器的氧化硅膜通过等离子体CVD法在450℃至700℃的温度下形成。在该半导体集成电路器件中，由MISFET形成的存储单元 用于数据传送，并且在存储单元形成区域中形成电容器，并且在逻辑电路形成区域中形成构成逻辑电路的n沟道MISFET和ap沟道MISFET。 结果，可以减少从氧化硅膜脱气的量。 因此，构成电容器的下电极的硅膜的表面上的硅晶粒的生长不受脱气的阻碍，能够增加电容。 此外，可以省略在形成氧化硅膜之后除去水分等的步骤，并且可以防止MISFET的性能劣化。

公开(公告)号：US06183044B2

公开(公告)日：2001-02-06

申请号：US09490062

申请日：2000-01-24

申请人： Toshiro Koyanagi ,  Koji Hiramatsu ,  Tsuyoshi Fujiwara ,  Yoshinobu Sawamoto ,  Toshiaki Iwasaki ,  Atsushi Hiroshige ,  Shunichi Katsumata

发明人： Toshiro Koyanagi ,  Koji Hiramatsu ,  Tsuyoshi Fujiwara ,  Yoshinobu Sawamoto ,  Toshiaki Iwasaki ,  Atsushi Hiroshige ,  Shunichi Katsumata

IPC分类号： B60N228

CPC分类号： B60N2/2821 ,  B60N2/289

摘要： A child seat is formed of a child seat main portion for holding a child having an engaging member, and a base on which the child seat main portion is detachably mounted. The base has a connecting portion to be connected to a vehicle, and a fixing member to be engageable with the engaging member of the child seat main portion. An engagement releasing member is installed in the base or the child seat main portion for releasing an engagement between the fixing member and the engaging member. Since the base can be connected to the vehicle without the child seat main portion, the child seat can be extremely simply fixed to the vehicle.

摘要翻译： 儿童座椅由用于保持具有接合构件的儿童的儿童座椅主体部分和儿童座椅主体部分可拆卸地安装在其上的基座形成。 基座具有连接到车辆的连接部分和可与儿童座椅主体部分的接合部件接合的固定部件。 接合释放构件安装在基座或儿童座椅主体部分中，用于释放固定构件和接合构件之间的接合。 由于基座可以连接到没有儿童座椅主要部分的车辆，所以儿童座椅可以非常简单地固定在车辆上。

公开(公告)号：US20120298319A1

公开(公告)日：2012-11-29

申请号：US13575390

申请日：2011-02-01

申请人： Tsuyoshi Fujiwara ,  Naohide Ogita ,  Takashi Kawamukai

发明人： Tsuyoshi Fujiwara ,  Naohide Ogita ,  Takashi Kawamukai

IPC分类号： D21H23/00 ,  D21F3/00 ,  D21H11/00

CPC分类号： D21C9/06 ,  B01D39/1607 ,  B01D39/18 ,  B01D67/0004 ,  B01D69/10 ,  B01D71/10 ,  B01D2239/0613 ,  B01D2239/0618 ,  B01D2239/10 ,  B01D2323/42 ,  D21H11/18 ,  D21H15/02 ,  Y10T428/249921 ,  Y10T428/298

摘要： The present invention relates to a method of producing a cellulose-fiber flat structure, the method including obtaining a cellulose-fiber flat structure by filtering a fine cellulose-fiber dispersion containing fine cellulose fibers having an average fiber diameter of 4 to 100 nm, using a filter material having a water permeability of not more than 100 ml/m2·s and an initial tensile modulus of 20 MPa or greater. The present invention is able to produce a cellulose-fiber flat structure by efficiently recovering fine cellulose fibers from a dispersion containing fine cellulose fibers having an average fiber diameter at the nano level. The method of producing a cellulose-fiber flat structure can also be applied to a continuous process.

摘要翻译： 纤维素纤维扁平结构体的制造方法技术领域本发明涉及纤维素纤维平坦结构体的制造方法，其特征在于，使用平均纤维直径为4〜100nm的细纤维素纤维的细纤维素纤维分散体， 透水度不大于100ml / m 2·s，初始拉伸弹性模量为20MPa以上的过滤材料。 本发明能够通过从包含平均纤维直径在纳米级的细纤维素纤维的分散体中有效地回收细纤维素纤维而制造纤维素纤维平坦结构。 纤维素纤维平坦结构的制造方法也可以应用于连续工序。

公开(公告)号：US07981761B2

公开(公告)日：2011-07-19

申请号：US12750402

申请日：2010-03-30

申请人： Toshinori Imai ,  Tsuyoshi Fujiwara ,  Hiroshi Ashihara ,  Akira Ootaguro ,  Yoshihiro Kawasaki

发明人： Toshinori Imai ,  Tsuyoshi Fujiwara ,  Hiroshi Ashihara ,  Akira Ootaguro ,  Yoshihiro Kawasaki

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L21/4763 ,  H01L21/70 ,  H01L21/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/28

CPC分类号： H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。