公开(公告)号：US20110128807A1

公开(公告)日：2011-06-02

申请号：US12697275

申请日：2010-01-31

申请人： Ashish Sharma ,  Lawrence F. Childs ,  Bikas Maiti ,  Manmohan Rana

发明人： Ashish Sharma ,  Lawrence F. Childs ,  Bikas Maiti ,  Manmohan Rana

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C7/08 ,  G11C7/227

摘要： A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled to the timing circuitry. The reference word line formed in the strap region.

摘要翻译： 存储器件包括存储器阵列，耦合到存储器阵列的检测电路和耦合到感测电路的定时电路。 定时电路产生感测触发信号以使能感测电路。 带状区域形成在存储器阵列附近。 参考字线耦合到定时电路。 在带区域中形成的参考字线。

公开(公告)号：US20110211382A1

公开(公告)日：2011-09-01

申请号：US12714528

申请日：2010-02-28

申请人： Ashish SHARMA ,  Bikas Maiti ,  Manmohan Rana

发明人： Ashish SHARMA ,  Bikas Maiti ,  Manmohan Rana

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C17/18 ,  G11C11/5692 ,  G11C17/12

摘要： A read-only memory for storing two data values using a single transistor includes a word line, a pair of bit lines, a select line, and a transistor to store data corresponding to each bit lines in the pair of bit lines. The gate terminal of the transistor is connected to the word line, a first diffusion terminal of the transistor is connected to one of the first bit line and the select line based on the first data value and a second diffusion terminal of the transistor is connected to one of the second bit line and the select line based on the second data value.

摘要翻译： 用于使用单个晶体管存储两个数据值的只读存储器包括字线，一对位线，选择线和晶体管，以存储对应于该对位线中的每个位线的数据。 晶体管的栅极端子连接到字线，晶体管的第一扩散端基于第一数据值连接到第一位线和选择线之一，并且晶体管的第二扩散端连接到 第二位线之一和基于第二数据值的选择线。

公开(公告)号：US08116153B2

公开(公告)日：2012-02-14

申请号：US12687847

申请日：2010-01-14

申请人： Manmohan Rana ,  Bikas Maiti ,  Ashish Sharma

发明人： Manmohan Rana ,  Bikas Maiti ,  Ashish Sharma

IPC分类号： G11C7/00

CPC分类号： G11C17/18 ,  G11C17/12

摘要： A Read Only Memory (ROM) device includes a ROM array, a row address decoder, a column address decoder, a column multiplexer, and a control circuit. Data is stored in bit cells in the ROM array. The control circuit generates control signals for reading the ROM. The row address decoder selects a word line. The column address decoder enables a bit line. The data is sensed from a bit cell corresponding to the selected word line and the enabled bit line by a corresponding sense amplifier and delivered on a data output pin of the ROM. The control signals for enabling the bit line and the sense amplifier operate at a higher voltage than supply voltage of the ROM. This reduces the ROM read time.

摘要翻译： 只读存储器（ROM）装置包括ROM阵列，行地址解码器，列地址解码器，列复用器和控制电路。 数据存储在ROM阵列中的位单元格中。 控制电路产生用于读取ROM的控制信号。 行地址解码器选择字线。 列地址解码器启用位线。 通过对应的读出放大器从对应于所选字线和使能位线的位单元中感测数据，并传送到ROM的数据输出引脚。 用于使位线和读出放大器的控制信号的工作电压高于ROM的电源电压。 这减少了ROM读取时间。

公开(公告)号：US07940545B2

公开(公告)日：2011-05-10

申请号：US12488624

申请日：2009-06-22

申请人： Ashish Sharma ,  Sanjeev Kumar Jain ,  Manmohan Rana

发明人： Ashish Sharma ,  Sanjeev Kumar Jain ,  Manmohan Rana

IPC分类号： G11C17/00

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.

摘要翻译： ROM包括ROM阵列，地址解码器，控制电路，预充电跟踪器，预充电电路，参考字线，参考位线和参考检测发生器。 控制电路产生用于读取ROM的控制信号。 地址解码器支持位线和字线。 预充电跟踪器产生可编程预充电信号，该预充电信号被提供给预充电电路，用于预充电使能的位线。 基于可编程预充电信号和用于跟踪使能字线的控制信号使能参考字线。 基于用于跟踪使能的位线的参考字线使能参考位线。 参考检测发生器基于参考位线，可编程预充电信号和用于读取对应于使能位线和字线的位单元的控制信号产生可编程感测信号。

公开(公告)号：US20090316464A1

公开(公告)日：2009-12-24

申请号：US12488624

申请日：2009-06-22

申请人： Ashish Sharma ,  Sanjeev Kumar Jain ,  Manmohan Rana

发明人： Ashish Sharma ,  Sanjeev Kumar Jain ,  Manmohan Rana

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.

摘要翻译： ROM包括ROM阵列，地址解码器，控制电路，预充电跟踪器，预充电电路，参考字线，参考位线和参考检测发生器。 控制电路产生用于读取ROM的控制信号。 地址解码器支持位线和字线。 预充电跟踪器产生可编程预充电信号，该预充电信号被提供给预充电电路，用于预充电使能的位线。 基于可编程预充电信号和用于跟踪使能字线的控制信号使能参考字线。 基于用于跟踪使能的位线的参考字线使能参考位线。 参考检测发生器基于参考位线，可编程预充电信号和用于读取对应于使能位线和字线的位单元的控制信号产生可编程感测信号。

公开(公告)号：US20160180924A1

公开(公告)日：2016-06-23

申请号：US14580171

申请日：2014-12-22

申请人： Paramjeet Singh ,  Manmohan Rana

发明人： Paramjeet Singh ,  Manmohan Rana

IPC分类号： G11C11/418

CPC分类号： G11C11/418 ,  G11C8/08

摘要： A method and apparatus in which word line drivers associated with memory word lines are selectively powered based on an active memory address reduces current consumption in a memory.

摘要翻译： 与存储器字线相关联的字线驱动器基于活动存储器地址选择性地供电的方法和装置减少了存储器中的电流消耗。

公开(公告)号：US20160033567A1

公开(公告)日：2016-02-04

申请号：US14451404

申请日：2014-08-04

申请人： Nishant Singh Thakur ,  Rakesh Pandey ,  Manmohan Rana

发明人： Nishant Singh Thakur ,  Rakesh Pandey ,  Manmohan Rana

IPC分类号： G01R31/28 ,  H03B5/32

CPC分类号： G01R31/282 ,  G01R31/2824 ,  H03B5/32

摘要： In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.

摘要翻译： 在集成电路中，时钟监视电路检测由片上晶体振荡器输出的模拟时钟信号何时稳定。 时钟监视电路使用包围跟踪器电路来监视模拟时钟信号的包络，并将包络的幅度与预定的振幅值进行比较。 当达到预定值并且信封在预定时间内保持稳定时，产生振荡器良好信号。 如果在另一预定时间内没有检测到振荡器正常信号，则可能产生振荡器故障信号。

公开(公告)号：US20150263039A1

公开(公告)日：2015-09-17

申请号：US14207482

申请日：2014-03-12

申请人： Paramjeet Singh ,  Shahab Akhtar ,  Manmohan Rana

发明人： Paramjeet Singh ,  Shahab Akhtar ,  Manmohan Rana

IPC分类号： H01L27/118

CPC分类号： H01L27/11807 ,  H01L2027/11812 ,  H01L2027/11816 ,  H01L2027/11866 ,  H01L2027/11881

摘要： A standard cell layout for a multiple input logic gate includes first through fourth parallel gate electrodes disposed over first and second active regions. The first and second gate electrodes are disposed on a first side of a first axis at first and second distances, respectively, from the first axis, and the third and fourth gate electrodes are disposed on a second side of the first axis at third and fourth distances, respectively, from the first axis. The first distance is greater than the second distance and the fourth distance is greater than the third distance. The third and fourth gate electrodes form a mirror image of the first and second gate electrodes about the first axis.

摘要翻译： 用于多输入逻辑门的标准单元布局包括设置在第一和第二有源区上的第一至第四并联栅电极。 第一和第二栅电极分别设置在第一轴上的第一和第二距离的第一侧上，并且第三和第四栅电极分别设置在第三轴和第四轴上的第一轴的第二侧上 距离第一轴。 第一距离大于第二距离，第四距离大于第三距离。 第三和第四栅电极围绕第一轴形成第一和第二栅电极的镜像。

公开(公告)号：US09142280B1

公开(公告)日：2015-09-22

申请号：US14452536

申请日：2014-08-06

申请人： Rakesh Pandey ,  Bharat K. Kumbhkar ,  Biswaprakash Navajeevan ,  Manmohan Rana

发明人： Rakesh Pandey ,  Bharat K. Kumbhkar ,  Biswaprakash Navajeevan ,  Manmohan Rana

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4094

CPC分类号： G11C11/40615 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4094 ,  G11C2211/4067

摘要： A circuit for configuring an external memory includes a memory controller, a register, an OR gate, first and second input/output (IO) pads, and pull-up and pull-down resistors. When the circuit is in a high power mode, the memory controller refreshes the external memory by providing reset and clock enable signals to the external memory by way of the first and second IO pads. When the circuit is in a low power mode, the pull-up and pull-down resistors configure the external memory in a self-refresh mode. When the circuit exits the low power mode, the first and second IO pads are powered on. The OR gate receives and provides a control signal output by the register to the external memory by way of the first IO pad, which keeps the external memory in the self-refresh mode.

摘要翻译： 用于配置外部存储器的电路包括存储器控制器，寄存器，或门，第一和第二输入/输出（IO）焊盘以及上拉和下拉电阻。 当电路处于高功率模式时，存储器控制器通过第一和第二IO焊盘向外部存储器提供复位和时钟使能信号来刷新外部存储器。 当电路处于低功耗模式时，上拉和下拉电阻将自身刷新模式下的外部存储器配置。 当电路退出低功耗模式时，第一个和第二个IO焊盘通电。 或门通过第一个IO接口接收寄存器输出的控制信号到外部存储器，保持外部存储器处于自刷新模式。

公开(公告)号：US08890602B2

公开(公告)日：2014-11-18

申请号：US13743324

申请日：2013-01-16

申请人： Samaksh Sinha ,  Manmohan Rana ,  Nishant Singh Thakur

发明人： Samaksh Sinha ,  Manmohan Rana ,  Nishant Singh Thakur

IPC分类号： H03K3/01

CPC分类号： G05F3/02 ,  G05F3/205

摘要： A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.

摘要翻译： 用于集成电路（IC）的阱偏置电路包括用于向阱偏压触点（n阱和p阱偏压触点）提供良好偏置电压（n阱和p阱偏置电压）的阱偏压调节器 ）当集成电路处于STOP和STANDBY模式时，IC的每个单元格。 在IC处于RUN和STOP模式和STANDBY模式时，开关连接在核心电源和阱偏压触点之间，用于连接和断开芯电源和阱偏压触点。 分别在IC处于RUN模式和STOP和STANDBY模式时，电压反相器电路和CMOS反相电路使能和禁止开关。