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公开(公告)号：US08890602B2
公开(公告)日：2014-11-18
申请号：US13743324
申请日：2013-01-16
IPC分类号： H03K3/01
摘要： A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
摘要翻译： 用于集成电路（IC）的阱偏置电路包括用于向阱偏压触点（n阱和p阱偏压触点）提供良好偏置电压（n阱和p阱偏置电压）的阱偏压调节器 ）当集成电路处于STOP和STANDBY模式时，IC的每个单元格。 在IC处于RUN和STOP模式和STANDBY模式时，开关连接在核心电源和阱偏压触点之间，用于连接和断开芯电源和阱偏压触点。 分别在IC处于RUN模式和STOP和STANDBY模式时，电压反相器电路和CMOS反相电路使能和禁止开关。
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公开(公告)号：US20140197883A1
公开(公告)日：2014-07-17
申请号：US13743324
申请日：2013-01-16
IPC分类号： G05F3/02
摘要： A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
摘要翻译： 用于集成电路（IC）的阱偏置电路包括用于向阱偏压触点（n阱和p阱偏压触点）提供良好偏置电压（n阱和p阱偏置电压）的阱偏压调节器 ）当集成电路处于STOP和STANDBY模式时，IC的每个单元格。 在IC处于RUN和STOP模式和STANDBY模式时，开关连接在核心电源和阱偏压触点之间，用于连接和断开芯电源和阱偏压触点。 分别在IC处于RUN模式和STOP和STANDBY模式时，电压反相器电路和CMOS反相电路使能和禁止开关。
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公开(公告)号：US08890495B2
公开(公告)日：2014-11-18
申请号：US13748598
申请日：2013-01-24
摘要： A power supply that provides a supply voltage to an integrated circuit (IC) includes high and low power regulators and a power management circuit. The high power regulator regulates the supply voltage at a first voltage level and the low power regulator is set to an inactive mode when the IC is in a RUN mode. When the IC transitions from the RUN mode to a STOP mode, the high power regulator stops regulating and the supply voltage is maintained at a second voltage level, while the lower power regulator is set to an active mode for regulating the supply voltage at a third voltage level. A fallback signal is generated when the supply voltage drops below a first threshold value after which the low power regulator is set in the inactive mode and the high power regulator is configured to regulate the supply voltage at a fourth voltage level.
摘要翻译： 向集成电路（IC）提供电源电压的电源包括高，低功率调节器和电源管理电路。 高功率稳压器在第一个电压电平下调节电源电压，当IC处于RUN模式时，低功耗调节器将被设置为无效模式。 当IC从RUN模式转换到STOP模式时，高功率调节器停止调节，并且电源电压保持在第二电压电平，而较低功率调节器设置为主动模式，用于调节第三个电源电压 电压电平。 当电源电压下降到第一阈值以下时，产生回退信号，在此之后将低功率调节器设置在非活动模式，并且高功率调节器被配置为在第四电压电平下调节电源电压。
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公开(公告)号：US20140203866A1
公开(公告)日：2014-07-24
申请号：US13748598
申请日：2013-01-24
IPC分类号： G05F1/10
摘要： A power supply that provides a supply voltage to an integrated circuit (IC) includes high and low power regulators and a power management circuit. The high power regulator regulates the supply voltage at a first voltage level and the low power regulator is set to an inactive mode when the IC is in a RUN mode. When the IC transitions from the RUN mode to a STOP mode, the high power regulator stops regulating and the supply voltage is maintained at a second voltage level, while the lower power regulator is set to an active mode for regulating the supply voltage at a third voltage level. A fallback signal is generated when the supply voltage drops below a first threshold value after which the low power regulator is set in the inactive mode and the high power regulator is configured to regulate the supply voltage at a fourth voltage level.
摘要翻译： 向集成电路（IC）提供电源电压的电源包括高，低功率调节器和电源管理电路。 高功率稳压器在第一个电压电平下调节电源电压，当IC处于RUN模式时，低功耗调节器将被设置为无效模式。 当IC从RUN模式转换到STOP模式时，高功率调节器停止调节，并且电源电压保持在第二电压电平，而较低功率调节器设置为主动模式，用于调节第三个电源电压 电压电平。 当电源电压下降到第一阈值以下时，产生回退信号，在此之后将低功率调节器设置在非活动模式，并且高功率调节器被配置为在第四电压电平下调节电源电压。
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公开(公告)号：US09323272B2
公开(公告)日：2016-04-26
申请号：US14318699
申请日：2014-06-30
IPC分类号： H03L7/00 , G05F3/16 , H03K3/3562 , H03K19/00
CPC分类号： G05F3/16 , H03K3/3562 , H03K19/0016
摘要： An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.
摘要翻译： 支持内部和外部稳压器以及各种模式（如低功耗模式或测试模式）的集成电路包括电压调节器选择电路和功率控制电路。 调节器选择电路根据两个引脚条件选择一个内部和外部稳压器。 功率控制电路控制与功率模式对应的稳压器的ON / OFF状态，包括上电复位，进入低功耗模式以及从低功耗模式唤醒。
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公开(公告)号：US09234936B1
公开(公告)日：2016-01-12
申请号：US14451404
申请日：2014-08-04
CPC分类号： G01R31/282 , G01R31/2824 , H03B5/32
摘要： In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.
摘要翻译： 在集成电路中，时钟监视电路检测由片上晶体振荡器输出的模拟时钟信号何时稳定。 时钟监视电路使用包围跟踪器电路来监视模拟时钟信号的包络，并将包络的幅度与预定的振幅值进行比较。 当达到预定值并且信封在预定时间内保持稳定时，产生振荡器良好信号。 如果在另一预定时间内没有检测到振荡器正常信号，则可能产生振荡器故障信号。
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公开(公告)号：US20160033567A1
公开(公告)日：2016-02-04
申请号：US14451404
申请日：2014-08-04
CPC分类号： G01R31/282 , G01R31/2824 , H03B5/32
摘要： In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.
摘要翻译： 在集成电路中，时钟监视电路检测由片上晶体振荡器输出的模拟时钟信号何时稳定。 时钟监视电路使用包围跟踪器电路来监视模拟时钟信号的包络，并将包络的幅度与预定的振幅值进行比较。 当达到预定值并且信封在预定时间内保持稳定时，产生振荡器良好信号。 如果在另一预定时间内没有检测到振荡器正常信号，则可能产生振荡器故障信号。
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公开(公告)号：US09252751B2
公开(公告)日：2016-02-02
申请号：US14269194
申请日：2014-05-04
IPC分类号： H03K3/02 , H03K3/012 , G11C16/28 , G11C16/14 , G11C17/16 , G11C17/18 , H03K3/037 , H03K17/22
CPC分类号： H03K3/012 , G11C5/147 , G11C16/14 , G11C16/28 , G11C17/16 , G11C17/18 , G11C29/021 , G11C29/028 , G11C2029/0407 , H03K3/0375 , H03K17/22 , H03K17/223
摘要： Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.
摘要翻译： 在引导期间，片上系统（SOC）中的多重复位可能会被避免，其中包括一系列在引导期间锁定修整值的锁存器，并保留 甚至在SOC复位事件期间的修整值。 SOC在引导期间或由于引导之外的任何原因退出复位时被阻止进入复位循环。 不依赖于任何调整值的上电复位比较器电路使锁存器能够自动清零锁存的微调值，如果其自身的电源电压低于预设电平。
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公开(公告)号：US20150378385A1
公开(公告)日：2015-12-31
申请号：US14318699
申请日：2014-06-30
IPC分类号： G05F3/16 , H03K3/038 , H03K3/3568 , H03K3/012
CPC分类号： G05F3/16 , H03K3/3562 , H03K19/0016
摘要： An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.
摘要翻译： 支持内部和外部稳压器以及各种模式（如低功耗模式或测试模式）的集成电路包括电压调节器选择电路和功率控制电路。 调节器选择电路根据两个引脚条件选择一个内部和外部稳压器。 功率控制电路控制与功率模式对应的稳压器的ON / OFF状态，包括上电复位，进入低功耗模式以及从低功耗模式唤醒。
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公开(公告)号：US20150318842A1
公开(公告)日：2015-11-05
申请号：US14269194
申请日：2014-05-04
CPC分类号： H03K3/012 , G11C5/147 , G11C16/14 , G11C16/28 , G11C17/16 , G11C17/18 , G11C29/021 , G11C29/028 , G11C2029/0407 , H03K3/0375 , H03K17/22 , H03K17/223
摘要： Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.
摘要翻译： 在引导期间，片上系统（SOC）中的多重复位可能会被避免，其中包括一系列在引导期间锁定修整值的锁存器，并保留 甚至在SOC复位事件期间的修整值。 SOC在引导期间或由于引导之外的任何原因退出复位时被阻止进入复位循环。 不依赖于任何调整值的上电复位比较器电路使锁存器能够自动清零锁存的微调值，如果其自身的电源电压低于预设电平。
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