公开(公告)号：US20130003882A1

公开(公告)日：2013-01-03

申请号：US13241944

申请日：2011-09-23

Applicant: ManoharRaju K.S.V. ,  Hiten ADVANI

Inventor： ManoharRaju K.S.V. ,  Hiten ADVANI

IPC: H04L27/00 ,  H03B1/00

CPC classification number: H02M3/156 ,  H04L25/0272 ,  H04L25/0286 ,  H04L25/03343 ,  H04L25/03878 ,  Y10T307/352 ,  Y10T307/549

Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.

Abstract translation: 预加重电路的实施例，用于预加强互补单端信号的方法的实施例，发射机的实施例以及通信系统的实施例。

公开(公告)号：US20130049797A1

公开(公告)日：2013-02-28

申请号：US13218134

申请日：2011-08-25

Applicant: Mayank Kumar SINGH ,  Daljeet KUMAR ,  Hiten ADVANI

Inventor： Mayank Kumar SINGH ,  Daljeet KUMAR ,  Hiten ADVANI

IPC: H03K19/003

CPC classification number: H03K19/00346 ,  H04L25/0278 ,  H04L25/0298

Abstract: An embodiment of an impedance calibration circuit and method, a device including an impedance calibration circuit, and a transmission link system.

Abstract translation: 阻抗校准电路和方法的实施例，包括阻抗校准电路的装置和传输链路系统。

公开(公告)号：US20130170288A1

公开(公告)日：2013-07-04

申请号：US13339580

申请日：2011-12-29

Applicant: Nishu KOHLI ,  Hiten ADVANI

Inventor： Nishu KOHLI ,  Hiten ADVANI

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/412

Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

Abstract translation: 存储单元由具有真实节点和补码节点的存储锁存器形成。 该单元包括可响应写入字线上的写入信号而工作的写入端口，以便将数据从写入位线写入锁存器，以及独立的读取端口，可响应读取字线上的读取信号读取数据， 锁存到读位线。 存储器单元的电路被配置为在读取存储器期间（其中电压反弹从同时写入到同一行中的另一个存储器单元）来解决补码节点处的电压反弹。

公开(公告)号：US20140009633A1

公开(公告)日：2014-01-09

申请号：US13542539

申请日：2012-07-05

Applicant: Sanjeev CHOPRA ,  Hiten ADVANI

Inventor： Sanjeev CHOPRA ,  Hiten ADVANI

IPC: H03L7/00 ,  H03K3/00 ,  H04N5/225 ,  H04L7/04 ,  H04B3/00

CPC classification number: H04L7/0012 ,  H04N5/225

Abstract: A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.

Abstract translation: 一种用于在源同步系统中利用多个可配置通道进行时钟和数据传输的系统和方法，其可利用来自另一源的时钟信号来解释从源接收的数据。 在一个实施例中，系统可以包括被配置为将至少一个时钟信号和至少一个数据信号发射到接收机设备的发射机。 接收机设备可以具有至少一个时钟通道和用于从发射机设备接收信号的至少一个数据通道。 时钟通道和数据通道可根据系统设计的要求以任何顺序排列。 在接收机中，在制造之后，每个数据通道可被配置成由任何时钟通道进行时钟控制。