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    Dual port register file memory cell with reduced susceptibility to noise during same row access
    3.
    发明授权
    Dual port register file memory cell with reduced susceptibility to noise during same row access 有权
    双端口寄存器文件存储单元，在同一行访问期间具有降低的噪声敏感性

    公开(公告)号：US08681534B2

    公开(公告)日：2014-03-25

    申请号：US13339580

    申请日：2011-12-29

    Applicant: Nishu Kohli ,  Hiten Advani

    Inventor： Nishu Kohli ,  Hiten Advani

    IPC: G11C11/00 ,  G11C8/00

    CPC classification number: G11C11/412

    Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

    Abstract translation: 存储单元由具有真实节点和补码节点的存储锁存器形成。 该单元包括可响应写入字线上的写入信号而工作的写入端口，以便将数据从写入位线写入锁存器，以及独立的读取端口，可响应读取字线上的读取信号读取数据， 锁存到读位线。 存储器单元的电路被配置为在读取存储器期间（其中电压反弹从同时写入到同一行中的另一个存储器单元）来解决补码节点处的电压反弹。

    Configurable lane architecture in source synchronous systems
    6.
    发明授权
    Configurable lane architecture in source synchronous systems 有权
    源同步系统中可配置的通道架构

    公开(公告)号：US08686754B2

    公开(公告)日：2014-04-01

    申请号：US13542539

    申请日：2012-07-05

    Applicant: Sanjeev Chopra ,  Hiten Advani

    Inventor： Sanjeev Chopra ,  Hiten Advani

    IPC: H03K19/177

    CPC classification number: H04L7/0012 ,  H04N5/225

    Abstract: A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.

    Abstract translation: 一种用于在源同步系统中利用多个可配置通道进行时钟和数据传输的系统和方法，其可利用来自另一源的时钟信号来解释从源接收的数据。 在一个实施例中，系统可以包括被配置为将至少一个时钟信号和至少一个数据信号发射到接收机设备的发射机。 接收机设备可以具有至少一个时钟通道和用于从发射机设备接收信号的至少一个数据通道。 时钟通道和数据通道可根据系统设计的要求以任何顺序排列。 在接收机中，在制造之后，每个数据通道可被配置成由任何时钟通道进行时钟控制。

    CONFIGURABLE LANE ARCHITECTURE IN SOURCE SYNCHRONOUS SYSTEMS
    7.
    发明申请
    CONFIGURABLE LANE ARCHITECTURE IN SOURCE SYNCHRONOUS SYSTEMS 有权
    来源同步系统中的可配置LANE架构

    公开(公告)号：US20140009633A1

    公开(公告)日：2014-01-09

    申请号：US13542539

    申请日：2012-07-05

    Applicant: Sanjeev CHOPRA ,  Hiten ADVANI

    Inventor： Sanjeev CHOPRA ,  Hiten ADVANI

    IPC: H03L7/00 ,  H03K3/00 ,  H04N5/225 ,  H04L7/04 ,  H04B3/00

    CPC classification number: H04L7/0012 ,  H04N5/225

    Abstract: A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.

    Abstract translation: 一种用于在源同步系统中利用多个可配置通道进行时钟和数据传输的系统和方法，其可利用来自另一源的时钟信号来解释从源接收的数据。 在一个实施例中，系统可以包括被配置为将至少一个时钟信号和至少一个数据信号发射到接收机设备的发射机。 接收机设备可以具有至少一个时钟通道和用于从发射机设备接收信号的至少一个数据通道。 时钟通道和数据通道可根据系统设计的要求以任何顺序排列。 在接收机中，在制造之后，每个数据通道可被配置成由任何时钟通道进行时钟控制。

    Timing skew measurement system
    8.
    发明授权
    Timing skew measurement system 有权
    定时偏移测量系统

    公开(公告)号：US07380230B2

    公开(公告)日：2008-05-27

    申请号：US11220386

    申请日：2005-09-06

    Applicant: Hiten Advani

    Inventor： Hiten Advani

    IPC: G06F17/50

    CPC classification number: G01R31/31725 ,  G01R31/31937

    Abstract: An improved timing skew measurement system includes a selector receiving a plurality of input signals whose relative skew is to be measured, a selection controller connected to the select inputs of the selector for selecting one of the input signals and a sequential logic element having a first input connected to the output of the selector. The system further includes a controllable clock generator capable of providing an adjustable clock edge position connected to a second input of the sequential logic element, the first and second inputs being associated by at least one defined timing relationship for correct operation of the sequential logic element, and an output analyzer having one input connected to the output of the sequential logic element, a first output connected to the input of the selection controller and a second output connected to the control input of the controllable clock generator.

    Abstract translation: 改进的定时偏移测量系统包括：接收多个输入信号的选择器，其相对偏差将被测量;连接到选择器的选择输入的选择控制器，用于选择输入信号之一;以及顺序逻辑元件，具有第一输入 连接到选择器的输出。 该系统还包括可控制时钟发生器，其能够提供连接到顺序逻辑元件的第二输入端的可调节时钟边沿位置，第一和第二输入通过至少一个定义的定时关系相关联，用于顺序逻辑元件的正确操作， 以及输出分析器，其具有连接到所述顺序逻辑元件的输出的一个输入，连接到所述选择控制器的输入的第一输出和连接到所述可控时钟发生器的控制输入的第二输出。

    DUAL PORT REGISTER FILE MEMORY CELL WITH REDUCED SUSCEPTIBILITY TO NOISE DURING SAME ROW ACCESS
    9.
    发明申请
    DUAL PORT REGISTER FILE MEMORY CELL WITH REDUCED SUSCEPTIBILITY TO NOISE DURING SAME ROW ACCESS 有权
    双端口注册文件存储单元在同样的访问期间具有降低的噪声可能性

    公开(公告)号：US20130170288A1

    公开(公告)日：2013-07-04

    申请号：US13339580

    申请日：2011-12-29

    Applicant: Nishu KOHLI ,  Hiten ADVANI

    Inventor： Nishu KOHLI ,  Hiten ADVANI

    IPC: G11C11/418 ,  G11C11/419

    CPC classification number: G11C11/412

    Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

    Abstract translation: 存储单元由具有真实节点和补码节点的存储锁存器形成。 该单元包括可响应写入字线上的写入信号而工作的写入端口，以便将数据从写入位线写入锁存器，以及独立的读取端口，可响应读取字线上的读取信号读取数据， 锁存到读位线。 存储器单元的电路被配置为在读取存储器期间（其中电压反弹从同时写入到同一行中的另一个存储器单元）来解决补码节点处的电压反弹。

    Timing skew measurement system
    10.
    发明申请
    Timing skew measurement system 有权
    定时偏移测量系统

    公开(公告)号：US20060136853A1

    公开(公告)日：2006-06-22

    申请号：US11220386

    申请日：2005-09-06

    Applicant: Hiten Advani

    Inventor： Hiten Advani

    IPC: G06F9/45 ,  G06F17/50

    CPC classification number: G01R31/31725 ,  G01R31/31937

    Abstract: An improved timing skew measurement system includes a selector receiving a plurality of input signals whose relative skew is to be measured, a selection controller connected to the select inputs of the selector for selecting one of the input signals and a sequential logic element having a first input connected to the output of the selector. The system further includes a controllable clock generator capable of providing an adjustable clock edge position connected to a second input of the sequential logic element, the first and second inputs being associated by at least one defined timing relationship for correct operation of the sequential logic element, and an output analyzer having one input connected to the output of the sequential logic element, a first output connected to the input of the selection controller and a second output connected to the control input of the controllable clock generator.

    Abstract translation: 改进的定时偏移测量系统包括：接收多个输入信号的选择器，其相对偏差将被测量;连接到选择器的选择输入的选择控制器，用于选择输入信号之一;以及顺序逻辑元件，具有第一输入 连接到选择器的输出。 该系统还包括可控制时钟发生器，其能够提供连接到顺序逻辑元件的第二输入端的可调节时钟边沿位置，第一和第二输入通过至少一个定义的定时关系相关联，用于顺序逻辑元件的正确操作， 以及输出分析器，其具有连接到所述顺序逻辑元件的输出的一个输入，连接到所述选择控制器的输入的第一输出和连接到所述可控时钟发生器的控制输入的第二输出。

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