公开(公告)号：US07211481B2

公开(公告)日：2007-05-01

申请号：US11060841

申请日：2005-02-18

申请人： Manoj Mehrotra ,  Lahir Shaik Adam ,  Song Zhao ,  Mahalingam Nandakumar

发明人： Manoj Mehrotra ,  Lahir Shaik Adam ,  Song Zhao ,  Mahalingam Nandakumar

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  Y10S438/902

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

摘要翻译： 本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。 源极/漏极区形成在PMOS区（102）的有源区中。 执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。 随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。 然后，在器件（108）上方形成封盖的多晶硅层。 执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。 由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

公开(公告)号：US20070287274A1

公开(公告)日：2007-12-13

申请号：US11451919

申请日：2006-06-13

申请人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

发明人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

IPC分类号： H01L21/425

CPC分类号： H01L21/2658 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.

摘要翻译： 公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F 2 O 2）中的至少一种与砷，磷和锑中的至少一种的注入相结合。 掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。 掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

公开(公告)号：US07557022B2

公开(公告)日：2009-07-07

申请号：US11451919

申请日：2006-06-13

申请人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

发明人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

IPC分类号： H01L21/425

CPC分类号： H01L21/2658 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.

摘要翻译： 公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F2）中的至少一种与砷，磷和锑中的至少一种的注入组合。 掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。 掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

公开(公告)号：US07274046B2

公开(公告)日：2007-09-25

申请号：US11144202

申请日：2005-06-02

申请人： Lahir Shaik Adam ,  Eddie H. Breashears ,  Alwin J. Tsao

发明人： Lahir Shaik Adam ,  Eddie H. Breashears ,  Alwin J. Tsao

IPC分类号： H01L29/72

CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L29/7833

摘要： The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

摘要翻译： 本发明提供一种用于制造三栅极半导体器件的三栅极低功率器件和方法。 三栅极器件包括位于高电压区域[460]内的高压栅极电介质[465]上的第一栅极[455]，位于低电压栅极电介质[450]内的第二栅极[435] 电压芯区域[440]和位于中间核心区域[480]内的第三栅极[475]。 一种制造方法包括在半导体衬底[415]上形成高电压栅介质层，在低电压核心区域[440]中将低剂量的氮[415a]注入到半导体衬底[415]中， 以及在所述低压芯区域[440]上形成核心栅介质层，包括在中间核心区域[480]上形成中间核心栅介质层[485]。

公开(公告)号：US07141480B2

公开(公告)日：2006-11-28

申请号：US10810419

申请日：2004-03-26

申请人： Lahir Shaik Adam ,  Eddie H. Breashears ,  Alwin J. Tsao

发明人： Lahir Shaik Adam ,  Eddie H. Breashears ,  Alwin J. Tsao

IPC分类号： H01L21/331

CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L29/7833

摘要： The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

摘要翻译： 本发明提供一种用于制造三栅极半导体器件的三栅极低功率器件和方法。 三栅极器件包括位于高电压区域[460]内的高压栅极电介质[465]上的第一栅极[455]，位于低电压栅极电介质[450]内的第二栅极[435] 电压芯区域[440]和位于中间核心区域[480]内的第三栅极[475]。 一种制造方法包括在半导体衬底[415]上形成高电压栅介质层，在低电压核心区域[440]中将低剂量的氮[415a]注入到半导体衬底[415]中， 以及在所述低压芯区域[440]上形成核心栅介质层，包括在中间核心区域[480]上形成中间核心栅介质层[485]。

公开(公告)号：US08372705B2

公开(公告)日：2013-02-12

申请号：US13013801

申请日：2011-01-25

申请人： Lahir Shaik Adam ,  Sanjay C Mehta ,  Balasubramanian S Haran ,  Bruce B. Doris

发明人： Lahir Shaik Adam ,  Sanjay C Mehta ,  Balasubramanian S Haran ,  Bruce B. Doris

IPC分类号： H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/4983 ,  H01L29/7843

摘要： CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

摘要翻译： 形成CMOS晶体管，其结合有在n沟道场效应晶体管的栅极侧壁上具有紧张应力间隔物的栅极，并且在ap沟道场效应晶体管的栅极侧壁上具有压缩应力间隔物，以在相应晶体管中提供差分应力通道以增加载流子迁移率 在各自的频道。

公开(公告)号：US20120086071A1

公开(公告)日：2012-04-12

申请号：US12902624

申请日：2010-10-12

申请人： Lahir Shaik Adam ,  Bruce B. Doris ,  Sanjay Mehta ,  Zhengmao Zhu

发明人： Lahir Shaik Adam ,  Bruce B. Doris ,  Sanjay Mehta ,  Zhengmao Zhu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7847

摘要： Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.

摘要翻译： 具有变形栅极区域的半导体衬底及其制造方法。 与具有变形的源极/漏极区域的器件相比，半导体衬底与不具有变形栅极区域的器件相比具有改进的器件性能和降低的掺杂剂损耗。