公开(公告)号：US07211481B2

公开(公告)日：2007-05-01

申请号：US11060841

申请日：2005-02-18

申请人： Manoj Mehrotra ,  Lahir Shaik Adam ,  Song Zhao ,  Mahalingam Nandakumar

发明人： Manoj Mehrotra ,  Lahir Shaik Adam ,  Song Zhao ,  Mahalingam Nandakumar

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  Y10S438/902

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

摘要翻译： 本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。 源极/漏极区形成在PMOS区（102）的有源区中。 执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。 随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。 然后，在器件（108）上方形成封盖的多晶硅层。 执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。 由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

公开(公告)号：US20060189048A1

公开(公告)日：2006-08-24

申请号：US11060841

申请日：2005-02-18

申请人： Manoj Mehrotra ,  Lahir Adam ,  Song Zhao ,  Mahalingam Nandakumar

发明人： Manoj Mehrotra ,  Lahir Adam ,  Song Zhao ,  Mahalingam Nandakumar

IPC分类号： H01L21/84

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  Y10S438/902

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

摘要翻译： 本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。 源极/漏极区形成在PMOS区（102）的有源区中。 执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。 随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。 然后，在器件（108）上形成封端的多晶硅层。 执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。 由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

公开(公告)号：US20070287274A1

公开(公告)日：2007-12-13

申请号：US11451919

申请日：2006-06-13

申请人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

发明人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

IPC分类号： H01L21/425

CPC分类号： H01L21/2658 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.

摘要翻译： 公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F 2 O 2）中的至少一种与砷，磷和锑中的至少一种的注入相结合。 掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。 掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

公开(公告)号：US07557022B2

公开(公告)日：2009-07-07

申请号：US11451919

申请日：2006-06-13

申请人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

发明人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

IPC分类号： H01L21/425

CPC分类号： H01L21/2658 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.

摘要翻译： 公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F2）中的至少一种与砷，磷和锑中的至少一种的注入组合。 掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。 掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

公开(公告)号：US06258644B1

公开(公告)日：2001-07-10

申请号：US09499719

申请日：2000-02-08

申请人： Mark S. Rodder ,  Manoj Mehrotra ,  Mahalingam Nandakumar

发明人： Mark S. Rodder ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC分类号： H01L218238

CPC分类号： H01L21/823814

摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.

摘要翻译： 用于高可靠性和高性能核心晶体管和输入输出晶体管的混合电压CMOS工艺，减少了掩模步骤。 在硅衬底（10）上形成栅叠层（30）。 对第一种和第二种进行离子注入，以在输入输出晶体管中产生掺杂分布（70,80,90,100）。

公开(公告)号：US20080308904A1

公开(公告)日：2008-12-18

申请号：US11763497

申请日：2007-06-15

申请人： P. R. Chidambaram ,  Srinivasan Chakravarthi ,  Mahalingam Nandakumar ,  Manoj Mehrotra ,  Amitabh Jain ,  Thomas D. Bonifield

发明人： P. R. Chidambaram ,  Srinivasan Chakravarthi ,  Mahalingam Nandakumar ,  Manoj Mehrotra ,  Amitabh Jain ,  Thomas D. Bonifield

IPC分类号： H01L21/425 ,  H01L29/36

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region.

摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底中提供C原子。 该方法还包括将In原子和p型掺杂剂注入被配置为具有碳原子的衬底的预定区域中。 该方法还包括对半导体衬底进行热退火以将预定区域转变为激活的掺杂区域。

公开(公告)号：US07678637B2

公开(公告)日：2010-03-16

申请号：US12209270

申请日：2008-09-12

申请人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

发明人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

摘要翻译： 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US20100133624A1

公开(公告)日：2010-06-03

申请号：US12696215

申请日：2010-01-29

申请人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

发明人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

摘要翻译： 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US08125035B2

公开(公告)日：2012-02-28

申请号：US12696215

申请日：2010-01-29

申请人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

发明人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

摘要翻译： 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US08101476B2

公开(公告)日：2012-01-24

申请号：US12541335

申请日：2009-08-14

申请人： Kanan Garg ,  Haowen Bu ,  Mahalingam Nandakumar ,  Song Zhao

发明人： Kanan Garg ,  Haowen Bu ,  Mahalingam Nandakumar ,  Song Zhao

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843 ,  H01L29/7845

摘要： A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.

摘要翻译： 一种用于形成具有不降低PMOS晶体管的高Si-H / N-H键比的NMOS晶体管的应力记忆增强的拉伸SiN应力层的方法。 CMOS集成电路通过NMOS源极和漏极注入而不是通过NMOS源极和漏极退火进行处理。 沉积SiN电介质层，使得FTIR光谱中Si-H峰与N-H峰的面积比大于7，并且SiN电介质的拉伸应力大于150MPa。 在沉积SiN电介质层之后对CMOS集成电路进行退火，并且从集成电路的至少一部分去除SiN介电层。