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    Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units
    3.
    发明授权
    Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units 有权
    用于在具有双执行单元的数字信号处理器上实现的有限脉冲响应滤波器算法

    公开(公告)号：US07107302B1

    公开(公告)日：2006-09-12

    申请号：US09570847

    申请日：2000-05-12

    申请人： Jose Fridman ,  Marc Hoffman

    发明人： Jose Fridman ,  Marc Hoffman

    IPC分类号： G06F17/10

    CPC分类号： G06F17/10 ,  H03H17/06 ,  H03H2218/10

    摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

    摘要翻译： 计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。 计算块包括寄存器文件和双执行单元。 执行单元包括用于在执行数字信号计算时增强性能的特征。 计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。 有限脉冲响应滤波算法在双执行单元上实现了高性能。

    Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
    5.
    发明授权
    Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation 有权
    计算核心执行多个操作DSP指令和较短长度的微控制器指令，无需执行开关操作

    公开(公告)号：US06820189B1

    公开(公告)日：2004-11-16

    申请号：US09570094

    申请日：2000-05-12

    申请人： Marc Hoffman ,  John Edmondson ,  Jose Fridman

    发明人： Marc Hoffman ,  John Edmondson ,  Jose Fridman

    IPC分类号： G06F930

    CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30149 ,  G06F9/3824 ,  G06F9/3867

    摘要： A computation core for executing programmed instructions includes an execution block for performing digital signal processor operations in response to digital signal processor instructions and for performing microcontroller operations in response to microcontroller instructions, a register file for storing operands for and results of the digital signal processor operations and the microcontroller operations, and control logic for providing control signals to the execution block and the register file in response to the instructions. The digital signal processor instructions each have a first length and the microcontroller instructions each have a second length that is less than the first length.

    摘要翻译： 用于执行编程指令的计算核心包括用于响应于数字信号处理器指令执行数字信号处理器操作并响应于微控制器指令执行微控制器操作的执行块，用于存储数字信号处理器操作的操作数和结果的寄存器文件 和微控制器操作，以及用于响应于指令向执行块和寄存器文件提供控制信号的控制逻辑。 数字信号处理器指令各自具有第一长度，并且微控制器指令各自具有小于第一长度的第二长度。

    Method for efficiently computing a fast fourier transform
    6.
    发明授权
    Method for efficiently computing a fast fourier transform 有权
    用于有效计算快速傅里叶变换的方法

    公开(公告)号：US07062523B1

    公开(公告)日：2006-06-13

    申请号：US09630258

    申请日：2000-08-01

    申请人： Marc Hoffman ,  Jose Fridman

    发明人： Marc Hoffman ,  Jose Fridman

    IPC分类号： G06F15/00

    CPC分类号： G06F17/142

    摘要： A method for computing an out of place FFT in which each stage of the FFT has an identical signal flow geometry. In each stage of the presently disclosed FFT method the group loop has been eliminated, the twiddle factor data is stored in bit-reversed manner, and the output data values are stored with a unity stride.

    摘要翻译： 一种计算不合格FFT的方法，其中FFT的每一级具有相同的信号流几何形状。 在目前公开的FFT方法的每个阶段中，组循环已被消除，旋转因子数据以位反转的方式存储，并且以单位步幅存储输出数据值。

    Despread signal recovery in digital signal processors
    9.
    发明授权
    Despread signal recovery in digital signal processors 有权
    数字信号处理器中的扩展信号恢复

    公开(公告)号：US07333530B1

    公开(公告)日：2008-02-19

    申请号：US09925889

    申请日：2001-08-06

    申请人： Rasekh Rifaat ,  Zvi Greenfield ,  Jose Fridman

    发明人： Rasekh Rifaat ,  Zvi Greenfield ,  Jose Fridman

    IPC分类号： H04B1/707

    CPC分类号： H04B1/7093

    摘要： A digital signal processor performs despread decoding in wireless telephone systems. Orthogonal codes are used to combine data signals into one overall coded signal which is transmitted. The orthogonal codes are used to retrieve individual data signals from the transmitted overall coded signal. Despread instructions are included in the digital signal processor functionality.

    摘要翻译： 数字信号处理器在无线电话系统中执行解扩解码。 正交码用于将数据信号组合成一个发送的总编码信号。 正交码用于从发送的总体编码信号中检索单个数据信号。 解扩指令包括在数字信号处理器功能中。

    Digital signal processor with bit FIFO
    10.
    发明授权
    Digital signal processor with bit FIFO 有权
    具有位FIFO的数字信号处理器

    公开(公告)号：US06332188B1

    公开(公告)日：2001-12-18

    申请号：US09187479

    申请日：1998-11-06

    申请人： Douglas Garde ,  Alexei Zatsman ,  Aryeh Lezerovitz ,  Zvi Greenfield ,  David R. Levine ,  Jose Fridman

    发明人： Douglas Garde ,  Alexei Zatsman ,  Aryeh Lezerovitz ,  Zvi Greenfield ,  David R. Levine ,  Jose Fridman

    IPC分类号： G06F9315

    CPC分类号： G06F9/30018 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30101

    摘要： A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.

    摘要翻译： 数字信号处理器包括具有算术逻辑单元，乘法器，移位器和寄存器文件的计算块。 计算块包括用于以位格式存储指令和操作数作为连续比特流的多个寄存器，并且利用比特传送机制在单个周期内传送多个寄存器之间的任意比特长度的比特字段和 移位器 多个寄存器可以是位于寄存器文件中的通用寄存器。 寄存器文件还可以包括至少一个控制信息寄存器，用于存储比特传送机制使用的控制信息。