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公开(公告)号：US07205920B2
公开(公告)日：2007-04-17
申请号：US11228114
申请日：2005-09-16
申请人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson , Atsushi Matamura , Andrew Abo
发明人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson , Atsushi Matamura , Andrew Abo
IPC分类号： H03M1/66
摘要： A sigma-delta digital-to-analog converter comprises a current digital-to-analog converter (IDAC) stage which generates a current depending on an input digital signal. An output current-to-voltage converter converts the generated signal to a voltage on a continuous-time basis. The amplifier used in the output current-to-voltage converter is chopper-stabilized. The converter can be single bit or multi-bit. The IDAC stage can be implemented with a pair of branches, a first branch comprising a first biasing current source and a second branch comprising a second biasing current source. The biasing current sources can be chopper-stabilized by connecting the bias current sources to the output current-to-voltage converter by a set of switches. The switches connect the biasing current sources to the output current-to-voltage converter in a first configuration and a second, reversed, configuration. This modulates flicker noise contributed by the bias current sources to the chopping frequency. from where it can be removed by filtering downstream of the current-to-voltage converter.
摘要翻译： Σ-Δ数模转换器包括根据输入数字信号产生电流的当前数模转换器（IDAC）级。 输出电流 - 电压转换器将产生的信号连续地转换成电压。 在输出电流 - 电压转换器中使用的放大器是斩波稳定的。 转换器可以是单位或多位。 IDAC级可以用一对分支来实现，第一分支包括第一偏置电流源和包括第二偏置电流源的第二分支。 通过一组开关将偏置电流源连接到输出电流 - 电压转换器，可以对偏置电流源进行斩波稳定。 开关将偏置电流源以第一配置和第二反向配置连接到输出电流 - 电压转换器。 这将调制由偏置电流源提供的闪烁噪声到斩波频率。 从那里可以通过对电流 - 电压转换器的下游进行滤波来去除。
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2.发明授权Feedback DAC chopper stabilization in a CT single-ended multi-bit sigma delta ADC 有权反馈DAC斩波稳定在CT单端多位Σ-ΔADC公开(公告)号：US07227481B2
公开(公告)日：2007-06-05
申请号：US11224457
申请日：2005-09-12
IPC分类号： H03M3/00
摘要： A multi-bit sigma-delta analog-to-digital converter (ADC) has a single-ended input for receiving an analog input signal. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a multibit digital feedback signal from a Flash ADC. The feedback current is summed with the input signal with the feedback current. The summed signal is integrated on a continuous-time basis. The IDAC is selectively connectable to the summing node via a first path and a second path. The first path transmits current from the IDAC to the summing node with a first polarity and the second path transmits current from the IDAC to the summing node with an inverted polarity. This can reduce flicker noise and can allow the converter to operate without any mid-scale biasing current sources.
摘要翻译： 多位Σ-Δ模数转换器（ADC）具有用于接收模拟输入信号的单端输入。 多位反馈电流数/模转换器（IDAC）根据来自闪存ADC的多位数字反馈信号产生多电平反馈电流。 反馈电流与具有反馈电流的输入信号相加。 累加信号在连续时间基础上进行积分。 IDAC可以经由第一路径和第二路径选择性地连接到求和节点。 第一路径将电流从IDAC发送到具有第一极性的求和节点，并且第二路径以反相极性将电流从IDAC发送到求和节点。 这可以降低闪烁噪声，并且可以允许转换器在没有任何中等偏置电流源的情况下工作。
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3.发明授权Differential front-end continuous-time sigma-delta ADC using chopper stabilization 有权差分前端连续时间Σ-ΔADC使用斩波稳定公开(公告)号：US07193545B2
公开(公告)日：2007-03-20
申请号：US11228113
申请日：2005-09-16
申请人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson
发明人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson
IPC分类号： H03M3/00
摘要： A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency FS and the chopping switches can operate at FS or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.
摘要翻译： 多位连续时间Σ-Δ模数转换器（ADC）具有接收模拟输入信号电流的差分输入级。 多位反馈电流数模转换器（IDAC）根据闪存ADC的数字反馈信号产生多电平反馈电流。 积分器具有差分输入，其通过多位IDAC产生的电流与输入信号电流的连续时间积分。 输入级还包括第一偏置电流源和在中等尺度条件下偏置输入级的第二偏置电流源。 第一求和节点连接到第一差分输入线，积分器的第一差分输入和第一输出分支。 第二求和节点连接到第二差分输入线，积分器和第二输出分支的第二差分输入。 一组斩波开关将偏置电流源以第一配置和第二反向配置交替地连接到求和节点。 转换器以频率F S S接收调制器时钟信号，并且斩波开关可以在F S或其二进制细分上工作。 积分放大器也可以斩波稳定。
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公开(公告)号：US07427887B2
公开(公告)日：2008-09-23
申请号：US11129240
申请日：2005-05-13
IPC分类号： H03K17/687
CPC分类号： H03K17/102 , H03K17/063 , H03K17/08142 , H03K17/6872
摘要： An open drain driver (7) selectively switches a MOSFET switch (MN1) which is passively held in the conducting state into the non-conducting state. The MOSFET switch (MN1) switches an AC analogue input signal on a main input terminal (3) to a main output terminal (4) and the gate of the MOSFET switch (MN1) is AC coupled by a capacitor (C1) to the drain thereof. The open drain driver (7) comprises a first MOSFET (MN2) and a second MOSFET (MN3) through which the gate of the MOSFET switch (MN1) is pulled to ground (Vss). The gate of the first MOSFET (MN2) is coupled to the supply voltage (VDD) for maintaining the first MOSFET (MN2) in the open state. A control signal is applied to the gate of the second MOSFET (MN3) for selectively operating the open drain driver (7) in the conducting state for operating the MOSFET switch (MN1) in the non-conducting state. When the second MOSFET (MN3) is in the non-conducting state, the first MOSFET (MN2) remains in the conducting state until the voltage on a coupling node (9) between the first and second MOSFETs (MN2,MN3) equals the difference between its gate voltage and its threshold voltage, at which stage, any over-voltages applied to the gate of the MOSFET switch (MN1) are divided between the first and second MOSFETs (MN2,MN3). A coupling diode (D1) coupling the coupling node (9) to the supply voltage (VDD) clamps the voltage on the coupling node (9) at the supply voltage (VDD) plus the conducting voltage of the diode (D1), in the event of the voltage on the coupling node (9) rising after the first MOSFET (MN2) has gone into the non-conducting state. The coupling node (9) may be capacitively coupled to the supply voltage (VDD) by a coupling capacitor instead of or as well as the diode (D1) for limiting the voltage on the coupling node (9).
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5.发明申请Differential front-end continuous-time sigma-delta ADC using chopper stabilisation 有权差分前端连续时间Σ-ΔADC使用斩波稳定公开(公告)号：US20060139192A1
公开(公告)日：2006-06-29
申请号：US11228113
申请日：2005-09-16
申请人： Paul Morrow , Maria del Mar Chamarro Marti , Colin Lyden , Mike Keane , Robert Adams , Richard O'Brien , Paschal Minogue , Hans Mansson
发明人： Paul Morrow , Maria del Mar Chamarro Marti , Colin Lyden , Mike Keane , Robert Adams , Richard O'Brien , Paschal Minogue , Hans Mansson
IPC分类号： H03M3/00
摘要： A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency FS and the chopping switches can operate at FS or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.
摘要翻译： 多位连续时间Σ-Δ模数转换器（ADC）具有接收模拟输入信号电流的差分输入级。 多位反馈电流数模转换器（IDAC）根据闪存ADC的数字反馈信号产生多电平反馈电流。 积分器具有差分输入，其通过多位IDAC产生的电流与输入信号电流的连续时间积分。 输入级还包括第一偏置电流源和在中等尺度条件下偏置输入级的第二偏置电流源。 第一求和节点连接到第一差分输入线，积分器的第一差分输入和第一输出分支。 第二求和节点连接到第二差分输入线，积分器和第二输出分支的第二差分输入。 一组斩波开关将偏置电流源以第一配置和第二反向配置交替地连接到求和节点。 转换器以频率F S S接收调制器时钟信号，并且斩波开关可以在F S或其二进制细分上工作。 积分放大器也可以斩波稳定。
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