公开(公告)号：US07205920B2

公开(公告)日：2007-04-17

申请号：US11228114

申请日：2005-09-16

申请人： Paul John Morrow ,  Maria del Mar Chamarro Marti ,  Colin G. Lyden ,  Mike Dominic Keane ,  Robert W. Adams ,  Richard Thomas O'Brien ,  Paschal Thomas Minogue ,  Hans Johan Olaf Mansson ,  Atsushi Matamura ,  Andrew Abo

发明人： Paul John Morrow ,  Maria del Mar Chamarro Marti ,  Colin G. Lyden ,  Mike Dominic Keane ,  Robert W. Adams ,  Richard Thomas O'Brien ,  Paschal Thomas Minogue ,  Hans Johan Olaf Mansson ,  Atsushi Matamura ,  Andrew Abo

IPC分类号： H03M1/66

CPC分类号： H03M3/34 ,  H03M3/502

摘要： A sigma-delta digital-to-analog converter comprises a current digital-to-analog converter (IDAC) stage which generates a current depending on an input digital signal. An output current-to-voltage converter converts the generated signal to a voltage on a continuous-time basis. The amplifier used in the output current-to-voltage converter is chopper-stabilized. The converter can be single bit or multi-bit. The IDAC stage can be implemented with a pair of branches, a first branch comprising a first biasing current source and a second branch comprising a second biasing current source. The biasing current sources can be chopper-stabilized by connecting the bias current sources to the output current-to-voltage converter by a set of switches. The switches connect the biasing current sources to the output current-to-voltage converter in a first configuration and a second, reversed, configuration. This modulates flicker noise contributed by the bias current sources to the chopping frequency. from where it can be removed by filtering downstream of the current-to-voltage converter.

摘要翻译： Σ-Δ数模转换器包括根据输入数字信号产生电流的当前数模转换器（IDAC）级。 输出电流 - 电压转换器将产生的信号连续地转换成电压。 在输出电流 - 电压转换器中使用的放大器是斩波稳定的。 转换器可以是单位或多位。 IDAC级可以用一对分支来实现，第一分支包括第一偏置电流源和包括第二偏置电流源的第二分支。 通过一组开关将偏置电流源连接到输出电流 - 电压转换器，可以对偏置电流源进行斩波稳定。 开关将偏置电流源以第一配置和第二反向配置连接到输出电流 - 电压转换器。 这将调制由偏置电流源提供的闪烁噪声到斩波频率。 从那里可以通过对电流 - 电压转换器的下游进行滤波来去除。

公开(公告)号：US07193545B2

公开(公告)日：2007-03-20

申请号：US11228113

申请日：2005-09-16

申请人： Paul John Morrow ,  Maria del Mar Chamarro Marti ,  Colin G. Lyden ,  Mike Dominic Keane ,  Robert W. Adams ,  Richard Thomas O'Brien ,  Paschal Thomas Minogue ,  Hans Johan Olaf Mansson

发明人： Paul John Morrow ,  Maria del Mar Chamarro Marti ,  Colin G. Lyden ,  Mike Dominic Keane ,  Robert W. Adams ,  Richard Thomas O'Brien ,  Paschal Thomas Minogue ,  Hans Johan Olaf Mansson

IPC分类号： H03M3/00

CPC分类号： H03M3/34 ,  H03M3/332 ,  H03M3/424 ,  H03M3/454

摘要： A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency FS and the chopping switches can operate at FS or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.

摘要翻译： 多位连续时间Σ-Δ模数转换器（ADC）具有接收模拟输入信号电流的差分输入级。 多位反馈电流数模转换器（IDAC）根据闪存ADC的数字反馈信号产生多电平反馈电流。 积分器具有差分输入，其通过多位IDAC产生的电流与输入信号电流的连续时间积分。 输入级还包括第一偏置电流源和在中等尺度条件下偏置输入级的第二偏置电流源。 第一求和节点连接到第一差分输入线，积分器的第一差分输入和第一输出分支。 第二求和节点连接到第二差分输入线，积分器和第二输出分支的第二差分输入。 一组斩波开关将偏置电流源以第一配置和第二反向配置交替地连接到求和节点。 转换器以频率F S S接收调制器时钟信号，并且斩波开关可以在F S或其二进制细分上工作。 积分放大器也可以斩波稳定。

公开(公告)号：US09668968B2

公开(公告)日：2017-06-06

申请号：US14429496

申请日：2013-10-04

申请人： Robert W. Adams

发明人： Robert W. Adams ,  Wayne C. Pollock

IPC分类号： A61K9/00 ,  A61K31/00 ,  A61K31/485 ,  B33Y10/00 ,  B33Y80/00 ,  B29C67/00 ,  A61L31/14 ,  A61L31/16 ,  B29K67/00 ,  B29L31/00

CPC分类号： A61K9/0024 ,  A61K31/485 ,  A61L31/08 ,  A61L31/148 ,  A61L31/16 ,  A61L2300/604 ,  A61L2420/02 ,  B29C64/112 ,  B29C64/386 ,  B29K2067/046 ,  B29K2995/0056 ,  B29K2995/006 ,  B29L2031/753 ,  B33Y10/00 ,  B33Y50/02 ,  B33Y80/00

摘要： A multi-step method of making a mammalian subcutaneous medical implant for releasing self-contained drugs on a controlled basis over at least a 3 day period includes depositing at least portions of one or more individual layers of the implant by at least one computer controlled 3-D printer. The 3-D printing method may be accomplished via an array of 3-D nozzles that deposit materials (such as plastics, thermoplastics, coating materials, drug-containing matrix materials, non-drug containing matrix materials, bonding materials, biodegradable materials and/or the like) in very small, precise portions. The materials may be deposited in liquid, powder, sheet or other forms. Non-implant forms may also be provided by the techniques disclosed herein.

公开(公告)号：US09427399B2

公开(公告)日：2016-08-30

申请号：US14822686

申请日：2015-08-10

申请人： Robert W. Adams

发明人： Robert W. Adams ,  Wayne C. Pollock

IPC分类号： A61K9/00 ,  A61K31/485 ,  B29C67/00 ,  B33Y10/00 ,  B33Y80/00 ,  B29K67/00

CPC分类号： A61K9/0024 ,  A61K31/485 ,  A61L31/08 ,  A61L31/148 ,  A61L31/16 ,  A61L2300/604 ,  A61L2420/02 ,  B29C64/112 ,  B29C64/386 ,  B29K2067/046 ,  B29K2995/0056 ,  B29K2995/006 ,  B29L2031/753 ,  B33Y10/00 ,  B33Y50/02 ,  B33Y80/00

摘要： A method (and the resulting product) of making a medical implant device for releasing self-contained drugs on a controlled basis wherein the method utilizes, at least in part, computer-controlled 3-D printing equipment to deposit via nozzles portions of one or more layers of the medical implant product. The implant has an outer impervious coating, an inner matrix core, an opening and an optional bonding layer.

摘要翻译： 制造用于在受控的基础上释放自给自足的药物的医疗植入装置的方法（以及最终的产品），其中该方法至少部分地利用计算机控制的3-D打印设备来经由喷嘴的一部分或 更多的医疗植入物产品层。 植入物具有外部不可渗透的涂层，内部矩阵芯，开口和可选的结合层。

公开(公告)号：US07095345B2

公开(公告)日：2006-08-22

申请号：US10936179

申请日：2004-09-08

申请人： Khiem Nguyen ,  Robert W. Adams

发明人： Khiem Nguyen ,  Robert W. Adams

IPC分类号： H03M1/10

CPC分类号： H03M3/386 ,  H03J1/0091 ,  H03J2200/10 ,  H03M3/458

摘要： A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

摘要翻译： 使用混合调谐电路，包括数字有限状态机和模拟调谐电路，以有效地保持连续时间积分器的RC乘积在过程，温度，电源和采样率变化之间恒定。 由于实施是连续的，跟踪比传统技术更准确。 使用精心挑选的时钟方案，该技术消除了反馈DAC中的符号间干扰。 该技术不使用参考频率，从而消除了用户识别参考频率的需要。

公开(公告)号：US6141671A

公开(公告)日：2000-10-31

申请号：US653125

申请日：1996-05-24

申请人： Robert W. Adams ,  Tom W. Kwan ,  Michael Coln

发明人： Robert W. Adams ,  Tom W. Kwan ,  Michael Coln

IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  G06F17/17

CPC分类号： H03H17/0628

摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

摘要翻译： 异步数字采样率转换器包括用于存储输入数据值的随机存取存储器和用于存储缩减的一组内插滤波器系数的只读存储器。 输入数据以输入采样率写入随机存取存储器。 输出样本由给定输入数据流的乘法/累加引擎提供，滤波器系数根据请求在输出频率下产生输出采样。 用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的一阶闭环系统 输出采样率。 这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。 还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。 该电路包括一种消除噪声的数字滞后形式。 通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。

公开(公告)号：US6041919A

公开(公告)日：2000-03-28

申请号：US221105

申请日：1998-12-23

申请人： Robert W. Adams

发明人： Robert W. Adams

IPC分类号： A45D34/04 ,  B44D3/12 ,  A45D44/18

CPC分类号： B44D3/127 ,  A45D34/046

摘要： A lid for a container having a spreadable fluid therein. The lid includes a less resilient portion having at least one hole defined therethrough and at least one more resilient portion overlapping the at least one hole of the less resilient portion. The more resilient portion has at least one slit grouping in registration with the at least one hole of the less resilient portion. The at least one slit grouping perforates the more resilient material.

摘要翻译： 用于其中具有可展开流体的容器的盖子。 盖子包括弹性较小的部分，其具有穿过其中限定的至少一个孔，并且至少一个弹性部分与较小弹性部分的至少一个孔重叠。 更具弹性的部分具有至少一个与较小弹性部分的至少一个孔对准的狭缝组。 至少一个狭缝组穿透更有弹性的材料。

公开(公告)号：US11065196B2

公开(公告)日：2021-07-20

申请号：US16021929

申请日：2018-06-28

申请人： Robert W. Adams

发明人： Robert W. Adams ,  Wayne C. Pollock

IPC分类号： A61K9/00 ,  B29C64/112 ,  B33Y10/00 ,  B33Y80/00 ,  A61L31/14 ,  A61L31/16 ,  B33Y50/02 ,  A61K31/485 ,  A61L31/08 ,  B29K67/00 ,  B29L31/00

摘要： A method (and the resulting product) of making a medical implant device for releasing self-contained drugs on a controlled basis wherein the method utilizes, at least in part, computer-controlled 3-D printing equipment to deposit via nozzles portions of one or more layers of the medical implant product. The implant has an outer impervious coating, an inner matrix core, an opening and an optional bonding layer.

公开(公告)号：US07205913B2

公开(公告)日：2007-04-17

申请号：US10127903

申请日：2002-04-23

申请人： Robert W. Adams ,  Douglas J. Mar ,  M. K. Stephen Yeung

发明人： Robert W. Adams ,  Douglas J. Mar ,  M. K. Stephen Yeung

IPC分类号： H03M5/00

CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464 ,  H03M3/502

摘要： An efficient data-directed scrambler is provided for processing digital signals having an unequally-weighted code. The data-directed scrambler includes inputs for receiving unequally-weighted bits of an input signal, outputs for supplying N scrambled bits of an output signal, and two or more scrambler columns connected in series between the inputs and the outputs. One or more of the scrambler columns includes a swapper cell and a digital fanout. Least significant bits in the unequally-weighted code are input to a swapper cell, and higher order bits in the unequally-weighted code are input to respective digital fanouts. In the other embodiments, an efficient data-directed scrambler is provided for processing digital signals having an equally-weighted code.

摘要翻译： 提供了一种用于处理具有不等加权码的数字信号的有效数据导向扰频器。 数据导向扰频器包括用于接收输入信号的不均衡加权比特的输入，用于提供输出信号的N个加扰比特的输出和串联连接在输入和输出之间的两个或更多个扰频列。 一个或多个扰频器列包括交换单元和数字扇出。 不平等加权码中的最低有效位被输入到交换单元，并且将不平等加权代码中的较高阶位输入到相应的数字扇出。 在其他实施例中，提供了一种有效的数据导向扰频器，用于处理具有同等加权码的数字信号。

公开(公告)号：US06531970B2

公开(公告)日：2003-03-11

申请号：US09876468

申请日：2001-06-07

申请人： Kevin J McLaughlin ,  Robert W. Adams

发明人： Kevin J McLaughlin ,  Robert W. Adams

IPC分类号： H03M700

CPC分类号： H03H17/0628

摘要： Methods and apparatus are provided for sample rate conversion in a system including two or more sample rate converters. The method includes the steps of providing an input clock and an output clock to each of the sample rate converters, measuring a sample rate ratio of the clocks in one of the sample rate converters, designated as a master, and controlling each of the sample rate converters with the sample rate ratio measured by the master. The measured sample rate ratio may be transmitted from the master to each of the other sample rate converters. This approach matches the group delays among the sample rate converters.