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1.发明授权Method and apparatus for performance enhancement in an asymmetrical semiconductor device 有权用于不对称半导体器件中的性能增强的方法和装置公开(公告)号：US07166897B2
公开(公告)日：2007-01-23
申请号：US10924650
申请日：2004-08-24
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
摘要翻译： 提出了一种在半导体器件中提供性能增强的方法和装置。 在一个实施例中，第一电流区域（64,76,23），沟道区域和第二电流区域（75,33,66）彼此相邻。 第二电流区域（75,33,66）具有比第一电流区域（64,76,23）中的第一元件的含量大的合金的第一元素的含量，其中第二电流区域（75， 所述第一元件的含量大于所述沟道区域中的所述第一元素的含量，所述合金还包括第二元素，所述第一元素具有第一价数，并且所述第二元素具有第二价数 。 此外，第一价数和第二价数之和为八。
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2.发明授权Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺公开(公告)号：US07238580B2
公开(公告)日：2007-07-03
申请号：US11043577
申请日：2005-01-26
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
摘要翻译： 半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。 第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。
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3.发明授权Semiconductor device having a plurality of different layers and method therefor 有权具有多个不同层的半导体器件及其方法公开(公告)号：US07271069B2
公开(公告)日：2007-09-18
申请号：US11111451
申请日：2005-04-21
申请人： Marius K. Orlowski , Vance H. Adams
发明人： Marius K. Orlowski , Vance H. Adams
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/78 , H01L29/7846 , H01L29/7848
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译： 可以使用具有选定的弹性模量的材料实现机械应力控制。 这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。 这些方法中的任何一种或多种可以组合使用。 机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。 此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。
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公开(公告)号：US07205202B2
公开(公告)日：2007-04-17
申请号：US11111450
申请日：2005-04-21
申请人： Marius K. Orlowski , Vance H. Adams
发明人： Marius K. Orlowski , Vance H. Adams
IPC分类号： H01L21/331
CPC分类号： H01L27/1203 , H01L21/84 , H01L21/86 , H01L29/7846
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译： 可以使用具有选定的弹性模量的材料实现机械应力控制。 这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。 这些方法中的任何一种或多种可以组合使用。 机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。 此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。
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公开(公告)号：US08314448B2
公开(公告)日：2012-11-20
申请号：US13105484
申请日：2011-05-11
IPC分类号： H01L29/80
CPC分类号： H01L29/66795 , H01L29/41791 , H01L29/785 , H01L2029/7858
摘要： Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region.
摘要翻译： 半导体结构的实施例包括第一电流电极区域，第二电流电极区域和沟道区域。 沟道区域位于第一电流电极区域和第二电流电极区域之间，沟道区域位于半导体结构的鳍结构中。 通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。
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公开(公告)号：US07927956B2
公开(公告)日：2011-04-19
申请号：US11609664
申请日：2006-12-12
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译： 提供了具有硅层的半导体衬底。 在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。 在硅层上形成非晶或多晶硅锗层。 或者，将锗注入硅层的顶部以形成非晶硅锗层。 然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。 然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。 在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。 或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。
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7.发明授权Electronic device including a fin-type transistor structure and a process for forming the electronic device 有权包括鳍型晶体管结构的电子器件和用于形成电子器件的工艺公开(公告)号：US07723805B2
公开(公告)日：2010-05-25
申请号：US11328594
申请日：2006-01-10
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译： 电子器件可以包括绝缘层和鳍型晶体管结构。 翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。 电介质层和间隔结构可以位于半导体鳍片和栅电极之间。 半导体鳍片可以包括沟道区域，其包括与位于与相对较低的VT相关联的部分和绝缘层之间的相对较高的VT相关联的部分。 在一个实施例中，电源电压低于通道区域的相对较高的VT。 还公开了一种用于形成电子器件的工艺。
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公开(公告)号：US20090115001A1
公开(公告)日：2009-05-07
申请号：US12347061
申请日：2008-12-31
IPC分类号： H01L29/78
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.
摘要翻译： 半导体器件的实施例包括半导体衬底，其具有主表面，间隔开的源极和漏极区域，其在主表面处由沟道区域分隔开，并且多层栅极结构位于沟道区域上方。 多层栅极结构包括与沟道区接触的栅极电介质层，包括覆盖栅极电介质层的金属氧化物的第一导体，覆盖第一导体的第二导体以及在栅极介电层和第二导体之间的杂质迁移抑制层 第一导体或第一导体与第二导体之间。
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公开(公告)号：US20070281446A1
公开(公告)日：2007-12-06
申请号：US11443627
申请日：2006-05-31
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/785
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.
摘要翻译： 半导体工艺和装置通过在第一区域（99）中暴露掩埋氧化物层（80）来提供平坦化的混合衬底（18），选择性地蚀刻掩埋氧化物层（80）以暴露第一半导体层 第二较小种子区域（98），然后从填充第二沟槽开口（100）的第一半导体层（70）的种子区域（98）外延生长第一外延半导体材料，并在暴露的绝缘体层上横向生长 80）以填充第一沟槽开口（99）的至少一部分，从而形成与第二半导体层（90）电隔离的第一外延半导体层（101）。 通过使用沉积的（100）硅并在外延生长（110）硅层（101）上形成第一SOI晶体管（161）在第一SOI层（90）上形成第一SOI晶体管器件（160），高性能CMOS器件 获得。
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公开(公告)号：US5985736A
公开(公告)日：1999-11-16
申请号：US949825
申请日：1997-10-14
申请人： Marius K. Orlowski , Karl Wimmer
发明人： Marius K. Orlowski , Karl Wimmer
IPC分类号： H01L21/32 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/32
摘要： Field isolation regions are formed using oxidation-resistant spacers or plugs that completely fill trenches within a semiconductor substrate prior to forming the field isolation regions. The spacers or plugs help to reduce encroachment of the field isolation regions under the spacers or plugs. The structure used as an oxidation mask for the field isolation process may include a silicon-containing member that is thicker than an overlying oxidation-resistant member. The thicker silicon-containing member may be capable of tolerating higher stress before defects in an underlying pad layer or substrate are formed.
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