公开(公告)号：US08722519B2

公开(公告)日：2014-05-13

申请号：US13182568

申请日：2011-07-14

Applicant: Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

Inventor： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

IPC: H01L27/07

CPC classification number: H01L21/02595 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract translation: 提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

公开(公告)号：US20080217714A1

公开(公告)日：2008-09-11

申请号：US11683236

申请日：2007-03-07

Applicant: Omar Zia ,  Ruiqi Tian

Inventor： Omar Zia ,  Ruiqi Tian

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/8249 ,  H01L21/84

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.

Abstract translation: 一种形成半导体器件的方法包括提供具有第一区域和第二区域的半导体衬底。 第一区域具有一个或多个第一元件，而第二区域具有一个或多个第二元件。 第一个元素与第二个元素不同。 定义了半导体器件上的瓦片特征的瓦片位置和第一瓦片表面区域。 半导体衬底的第一区域和第二区域都形成有源半导体层。 使用负色调掩模在瓷砖位置的有源半导体层中形成第一沟槽。 第一沟槽具有第一深度并且形成瓷砖特征的至少一部分。 使用正色调掩模在有源半导体层中形成第二沟槽。 第二沟槽具有与第一深度不同的第二深度。

公开(公告)号：US07109051B2

公开(公告)日：2006-09-19

申请号：US10989940

申请日：2004-11-15

Applicant: Nigel G. Cave ,  Omar Zia

Inventor： Nigel G. Cave ,  Omar Zia

IPC: H01L21/00 ,  H01L21/338

CPC classification number: H01L27/144 ,  H01L27/15

Abstract: A method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device portion. A semiconductor layer is epitaxially grown overlying an exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region. At least a portion of an electronic device is formed on the active semiconductor layer within the electronic device portion of the semiconductor substrate. The method further includes forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device.

公开(公告)号：US07098090B2

公开(公告)日：2006-08-29

申请号：US10989947

申请日：2004-11-15

Applicant: Omar Zia ,  Lawrence Cary Gunn, III

Inventor： Omar Zia ,  Lawrence Cary Gunn, III

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A method for integrating first and second type devices on a semiconductor substrate includes forming openings within an active semiconductor layer of a dual semiconductor-on-insulator in first and second regions of the semiconductor substrate. First and second non-MOS transistor device implant regions are formed within portions of an intermediate semiconductor layer underlying first and second openings, respectively, in a first device portion, filled with a fill material and planarized. A top surface portion of the active semiconductor layer disposed in-between the first and second openings is exposed, first and second low dose non-MOS transistor device well regions are formed in respective first and second portions of the intermediate semiconductor layer underlying a region in-between the first and second openings. The method further includes forming a salicide blocking layer, forming first and second contact vias within the fill material of the first and second openings, respectively, exposing a portion of the underlying intermediate semiconductor layer, forming first and second non-MOS transistor device contact regions in exposed portions of the intermediate semiconductor layer, and saliciding the semiconductor substrate, the salicide blocking layer preventing salicidation of the first and second low dose non-MOS transistor device well regions.

公开(公告)号：US20060105508A1

公开(公告)日：2006-05-18

申请号：US10989947

申请日：2004-11-15

Applicant: Omar Zia ,  Lawrence Gunn

Inventor： Omar Zia ,  Lawrence Gunn

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A method for integrating first and second type devices on a semiconductor substrate includes forming openings within an active semiconductor layer of a dual semiconductor-on-insulator in first and second regions of the semiconductor substrate. First and second non-MOS transistor device implant regions are formed within portions of an intermediate semiconductor layer underlying first and second openings, respectively, in a first device portion, filled with a fill material and planarized. A top surface portion of the active semiconductor layer disposed in-between the first and second openings is exposed, first and second low dose non-MOS transistor device well regions are formed in respective first and second portions of the intermediate semiconductor layer underlying a region in-between the first and second openings. The method further includes forming a salicide blocking layer, forming first and second contact vias within the fill material of the first and second openings, respectively, exposing a portion of the underlying intermediate semiconductor layer, forming first and second non-MOS transistor device contact regions in exposed portions of the intermediate semiconductor layer, and saliciding the semiconductor substrate, the salicide blocking layer preventing salicidation of the first and second low dose non-MOS transistor device well regions.

Abstract translation: 一种用于在半导体衬底上集成第一和第二类型器件的方法包括在半导体衬底的第一和第二区域中的双绝缘绝缘体半导体有源半导体层内形成开口。 第一和第二非MOS晶体管器件注入区分别形成在填充有填充材料并且被平坦化的第一器件部分中的分别位于第一和第二开口下方的中间半导体层的部分内。 设置在第一和第二开口之间的有源半导体层的顶表面部分被暴露，第一和第二低剂量非MOS晶体管器件阱区域形成在中间半导体层的相应的第一和第二部分中， - 在第一和第二开口之间。 该方法还包括形成自对准硅化物阻挡层，分别在第一和第二开口的填充材料内形成第一和第二接触通孔，暴露下面的中间半导体层的一部分，形成第一和第二非MOS晶体管器件接触区域 在中间半导体层的露出部分中，对半导体衬底进行水杨酸化处理，防止第一和第二低剂量非MOS晶体管器件阱区域的水化作用。

公开(公告)号：US07435639B2

公开(公告)日：2008-10-14

申请号：US11443627

申请日：2006-05-31

Applicant: Brian A. Winstead ,  Omar Zia ,  Mariam G. Sadaka ,  Marius K. Orlowski

Inventor： Brian A. Winstead ,  Omar Zia ,  Mariam G. Sadaka ,  Marius K. Orlowski

IPC: H01L21/8238

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/785

Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.

Abstract translation: 半导体工艺和装置通过在第一区域（99）中暴露掩埋氧化物层（80）来提供平坦化的混合衬底（18），选择性地蚀刻掩埋氧化物层（80）以暴露第一半导体层 第二较小种子区域（98），然后从填充第二沟槽开口（100）的第一半导体层（70）的种子区域（98）外延生长第一外延半导体材料，并在暴露的绝缘体层上横向生长 80）以填充第一沟槽开口（99）的至少一部分，从而形成与第二半导体层（90）电隔离的第一外延半导体层（101）。 通过使用沉积的（100）硅并在外延生长（110）硅层（101）上形成第一SOI晶体管（161）在第一SOI层（90）上形成第一SOI晶体管器件（160），高性能CMOS器件 获得。

公开(公告)号：US20080168418A1

公开(公告)日：2008-07-10

申请号：US11651253

申请日：2007-01-08

Applicant: Omar Zia ,  Nigel Cave ,  Venkat Kolagunta ,  Ruiqi Tian ,  Edward O. Travis

Inventor： Omar Zia ,  Nigel Cave ,  Venkat Kolagunta ,  Ruiqi Tian ,  Edward O. Travis

IPC: G06F17/50

CPC classification number: H01L21/84 ,  G06F2217/12 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/66651 ,  Y02P90/265

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Abstract translation: 提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301） （b）从第一数据集导出第一沟槽CMP掩模组（307）和至少一个外延生长掩模组（321,331），其中所述至少一个外延生长掩模组对应于存在的瓦片（305,307） 在第一（203）和第二（207）不同的半导体表面上; （c）重新配置第一沟槽CMP掩模组以考虑至少一个外延生长掩模组，由此限定第二沟槽CMP掩模组（308），其中第二沟槽CMP掩模组限定一组沟槽CMP瓦片; 和（d）使用第二沟槽CMP掩模组来制造半导体器件。

公开(公告)号：US20080164559A1

公开(公告)日：2008-07-10

申请号：US11650253

申请日：2007-01-04

Applicant: Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

Inventor： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

IPC: H01L21/763 ,  H01L29/02

CPC classification number: H01L21/02595 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract translation: 提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

公开(公告)号：US20060105488A1

公开(公告)日：2006-05-18

申请号：US10988963

申请日：2004-11-15

Applicant: Omar Zia ,  Nigel Cave ,  Lawrence Gunn

Inventor： Omar Zia ,  Nigel Cave ,  Lawrence Gunn

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L27/0617 ,  H01L21/84

Abstract: A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.

Abstract translation: 半导体结构在同一集成电路上具有波导晶体管。 一种沟槽隔离技术用于限定晶体管区域，另一种用于优化波导的横向边界。 波导和晶体管都具有可以单独优化的具有衬垫的沟槽。 晶体管具有用于源/漏触点的自对准硅。 在该过程中，在波导上使用自对准硅化物块以防止波导的不需要的区域中的自对准硅化物形成。 用于波导的沟槽的深度可以低于用于晶体管隔离的沟槽的深度。 沟槽隔离深度可以通过可以是相对于顶部半导体层可选择性蚀刻的薄氧化物层或缓冲层的蚀刻停止区域来设置，并且可以用作用于生长顶部半导体层的种子层。

公开(公告)号：US07785983B2

公开(公告)日：2010-08-31

申请号：US11683236

申请日：2007-03-07

Applicant: Omar Zia ,  Ruiqi Tian

Inventor： Omar Zia ,  Ruiqi Tian

IPC: H01L21/76 ,  H01L21/336

CPC classification number: H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/8249 ,  H01L21/84

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.

Abstract translation: 一种形成半导体器件的方法包括提供具有第一区域和第二区域的半导体衬底。 第一区域具有一个或多个第一元件，而第二区域具有一个或多个第二元件。 第一个元素与第二个元素不同。 定义了半导体器件上的瓦片特征的瓦片位置和第一瓦片表面区域。 半导体衬底的第一区域和第二区域都形成有源半导体层。 使用负色调掩模在瓷砖位置的有源半导体层中形成第一沟槽。 第一沟槽具有第一深度并且形成瓷砖特征的至少一部分。 使用正色调掩模在有源半导体层中形成第二沟槽。 第二沟槽具有与第一深度不同的第二深度。