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1.发明授权Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺公开(公告)号：US07238580B2
公开(公告)日：2007-07-03
申请号：US11043577
申请日：2005-01-26
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
摘要翻译： 半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。 第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。
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2.发明授权Method and apparatus for performance enhancement in an asymmetrical semiconductor device 有权用于不对称半导体器件中的性能增强的方法和装置公开(公告)号：US07166897B2
公开(公告)日：2007-01-23
申请号：US10924650
申请日：2004-08-24
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
摘要翻译： 提出了一种在半导体器件中提供性能增强的方法和装置。 在一个实施例中，第一电流区域（64,76,23），沟道区域和第二电流区域（75,33,66）彼此相邻。 第二电流区域（75,33,66）具有比第一电流区域（64,76,23）中的第一元件的含量大的合金的第一元素的含量，其中第二电流区域（75， 所述第一元件的含量大于所述沟道区域中的所述第一元素的含量，所述合金还包括第二元素，所述第一元素具有第一价数，并且所述第二元素具有第二价数 。 此外，第一价数和第二价数之和为八。
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3.发明授权Semiconductor device having a plurality of different layers and method therefor 有权具有多个不同层的半导体器件及其方法公开(公告)号：US07271069B2
公开(公告)日：2007-09-18
申请号：US11111451
申请日：2005-04-21
申请人： Marius K. Orlowski , Vance H. Adams
发明人： Marius K. Orlowski , Vance H. Adams
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/78 , H01L29/7846 , H01L29/7848
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译： 可以使用具有选定的弹性模量的材料实现机械应力控制。 这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。 这些方法中的任何一种或多种可以组合使用。 机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。 此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。
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公开(公告)号：US07205202B2
公开(公告)日：2007-04-17
申请号：US11111450
申请日：2005-04-21
申请人： Marius K. Orlowski , Vance H. Adams
发明人： Marius K. Orlowski , Vance H. Adams
IPC分类号： H01L21/331
CPC分类号： H01L27/1203 , H01L21/84 , H01L21/86 , H01L29/7846
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译： 可以使用具有选定的弹性模量的材料实现机械应力控制。 这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。 这些方法中的任何一种或多种可以组合使用。 机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。 此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。
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5.发明申请SEMICONDUCTOR DEVICE INCLUDING AN ACTIVE REGION AND TWO LAYERS HAVING DIFFERENT STRESS CHARACTERISTICS 有权包括活性区域和具有不同应力特性的两层的半导体器件公开(公告)号：US20140054704A1
公开(公告)日：2014-02-27
申请号：US14063459
申请日：2013-10-25
IPC分类号： H01L29/06
CPC分类号： H01L29/0642 , H01L21/823412 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/7842 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
摘要翻译： 集成电路包括包括器件的有源区的器件，其中器件的有源区包括具有横向和横向方向的沟道区。 器件还包括与有源区相邻的有源区的隔离区，该隔离区位于有源区域的横向方向，其中隔离区域包括位于与沟道区域横向的第一区域。 隔离区域还包括位于从第一区域的横向方向上的第二区域。 隔离区域的第一区域处于第一类型的应力处，并且隔离区域的第二区域是在第一类型的较小应力下或在与第一类型相反的第二类型的应力下。
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6.发明授权Electronic device including a transistor structure having an active region adjacent to a stressor layer 有权电子器件包括具有与应力层相邻的有源区的晶体管结构公开(公告)号：US07714318B2
公开(公告)日：2010-05-11
申请号：US12180818
申请日：2008-07-28
IPC分类号： H01L29/06
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。
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7.发明授权Semiconductor device including an active region and two layers having different stress characteristics 有权半导体器件包括具有不同应力特性的有源区和两层公开(公告)号：US08569858B2
公开(公告)日：2013-10-29
申请号：US11613326
申请日：2006-12-20
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/0642 , H01L21/823412 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/7842 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
摘要翻译： 集成电路包括包括器件的有源区的器件，其中器件的有源区包括具有横向和横向方向的沟道区。 器件还包括与有源区相邻的有源区的隔离区，该隔离区位于有源区域的横向方向，其中隔离区域包括位于与沟道区域横向的第一区域。 隔离区域还包括位于从第一区域的横向方向上的第二区域。 隔离区域的第一区域处于第一类型的应力处，并且隔离区域的第二区域是在第一类型的较小应力下或在与第一类型相反的第二类型的应力下。
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8.发明授权Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors 失效集成源极/漏极应力和半导体介电层应力的半导体工艺公开(公告)号：US07538002B2
公开(公告)日：2009-05-26
申请号：US11361171
申请日：2006-02-24
申请人： Da Zhang , Vance H. Adams , Bich-Yen Nguyen , Paul A. Grudowski
发明人： Da Zhang , Vance H. Adams , Bich-Yen Nguyen , Paul A. Grudowski
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.
摘要翻译： 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。
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公开(公告)号：US09847389B2
公开(公告)日：2017-12-19
申请号：US14063459
申请日：2013-10-25
IPC分类号： H01L21/70 , H01L29/06 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/78
CPC分类号： H01L29/0642 , H01L21/823412 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/7842 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
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10.发明申请ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION ADJACENT TO A STRESSOR LAYER 有权包括具有活动区域的晶体管结构的电子器件与压力层相邻公开(公告)号：US20080296633A1
公开(公告)日：2008-12-04
申请号：US12180818
申请日：2008-07-28
IPC分类号： H01L27/088
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。
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