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1.发明申请Method to Prevent Operand Data with No Locality from Polluting the Data Cache 审中-公开防止无地点操作数据污染数据缓存的方法公开(公告)号：US20080065834A1
公开(公告)日：2008-03-13
申请号：US11531288
申请日：2006-09-13
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F9/3832 , G06F12/123 , G06F2212/6028
摘要： A computer system with the means to identify based on the instruction being decoded that the operand data that this instruction will access by its nature will not have locality of access and should be installed in the cache in such a way that each successive line brought into the data cache that hits the same congruence class should be placed in the same set as to not disturb the locality of the data that resided in the cache prior to the execution of the instruction that accessed the data that will not have locality of access.
摘要翻译： 一种具有根据正在被解码的指令识别的手段的计算机系统，该指令本身将访问的操作数数据将不具有访问的位置，并且应该以这样的方式安装在每个连续的行中， 在同一个集合中的数据高速缓存应放置在相同的集合中，以便在执行访问不具有访问地址的数据的指令之前，不要干扰驻留在缓存中的数据的位置。
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2.发明授权公开(公告)号：US07035986B2
公开(公告)日：2006-04-25
申请号：US10435967
申请日：2003-05-12
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30043 , G06F12/0851 , G06F12/0857
摘要： An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced directory lookup structure. A same line detection unit receives a plurality of first instruction fields and a plurality of second instruction fields. The same line detection unit generates a same line signal in response to the first instruction fields and the second instruction fields. The cache storage simultaneously reads data from a single line in the cache storage in response to the same line signal.
摘要翻译： 本发明的一个实施例是用于提供对多个请求的同一数据的同时访问的处理器。 处理器包括具有地址分片目录查找结构的高速缓冲存储器。 同一行检测单元接收多个第一指令字段和多个第二指令字段。 相同的行检测单元响应于第一指令字段和第二指令字段产生相同的行信号。 高速缓存存储器同时响应于相同的线路信号从缓存存储器中的单个行读取数据。
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公开(公告)号：US08285941B2
公开(公告)日：2012-10-09
申请号：US12036476
申请日：2008-02-25
IPC分类号： G06F12/06
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
摘要翻译： 提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。 系统包括步幅图案检测器，用于检测作为连续高速缓存访问之间的差异的字节量的步幅大小的步幅图案。 系统还包括置信柜台。 该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。 该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。 系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。
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4.发明申请SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER 失效用于提供可编程QUIESCE FILTERING寄存器的系统，方法和计算机程序产品公开(公告)号：US20090216929A1
公开(公告)日：2009-08-27
申请号：US12037808
申请日：2008-02-26
IPC分类号： G06F13/24
CPC分类号： G06F9/4812
摘要： A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.
摘要翻译： 一种用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品。 该方法包括在处理器处接收静止中断请求。 处理器正在以一种模式执行。 识别与该模式相关联的过滤区域。 确定处理器是否可以过滤停顿中断请求。 该确定响应于过滤区域和可编程过滤寄存器的内容，用于指示接收处理器执行的过滤异常。 响应于确定可以对请求进行过滤，过滤掉静默中断请求。
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5.发明授权Facilitating quiesce operations within a logically partitioned computer system 失效在逻辑分区的计算机系统中促进停顿操作公开(公告)号：US08407701B2
公开(公告)日：2013-03-26
申请号：US12822818
申请日：2010-06-24
CPC分类号： G06F9/52
摘要： A facility is provided for processing to distinguish between a full conventional (or total system) quiesce request within a logically partitioned computer system, which requires all processors of the computer system to remain quiesced for the duration of the quiesce-related operation, and a new early-release conventional quiesce request, which is associated with fast-quiesce request utilization. In accordance with the facility, once all processors have quiesced responsive to a pending quiesce request sequence, the processors are allowed to block early-release conventional quiesce interrupts and to continue processing if there is no total system quiesce request in the pending quiesce request sequence.
摘要翻译： 提供了一种用于处理以区分逻辑分区的计算机系统内的完全常规（或整个系统）静默请求的设施，其要求计算机系统的所有处理器在静默相关操作期间保持静止，并且新的 早期发布常规静默请求，这与快速静默请求利用相关。 根据该设施，一旦所有处理器对待处理的静默请求序列作出响应，则处理器被允许阻止早期释放常规停顿中断，并且如果在暂停停顿请求序列中没有总系统静默请求，则继续处理。
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6.发明申请SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER 有权用于提供可编程QUIESCE FILTERING寄存器的系统，方法和计算机程序产品公开(公告)号：US20120144154A1
公开(公告)日：2012-06-07
申请号：US13372603
申请日：2012-02-14
IPC分类号： G06F12/10
CPC分类号： G06F9/4812
摘要： Storing translation lookaside buffer (TLB) entries are in a TLB1 at the processor. The TLB1 includes entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode. A quiesce interruption request is received at the processor that includes a requesting zone indicator. The processor is either executing in the host mode and has no zone or in the guest mode with the current zone. The requesting zone indicator and the contents of a programmable filtering register that indicates exceptions to filtering performed by the processor is used to determine if filtering should be performed. The quiesce interruption request may be filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.
摘要翻译： 存储翻译后备缓冲区（TLB）条目位于处理器的TLB1中。 TLB1包括与在当前区域中以访客模式执行的程序的主存储访问相关联的条目和与以主机模式执行的固件的主存储访问相关联的条目。 在包括请求区域指示符的处理器处接收到静默中断请求。 处理器正在主机模式下执行，并且没有区域，或者在访问模式下使用当前区域。 请求区域指示符和指示处理器执行的过滤异常的可编程过滤寄存器的内容用于确定是否应执行过滤。 即使模式从客户模式切换到主机模式，也可以基于请求区域指示符来过滤停顿中断请求。
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7.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CROSS-INVALIDATION HANDLING IN A MULTI-LEVEL PRIVATE CACHE 失效在多层次私有缓存中进行交叉处理的方法，系统和计算机程序产品公开(公告)号：US20090240889A1
公开(公告)日：2009-09-24
申请号：US12051736
申请日：2008-03-19
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译： 提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。 该系统包括一个处理器。 处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。 该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。 每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。 该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。 响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。
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8.发明授权System, method and computer program product for providing a programmable quiesce filtering register 失效用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品公开(公告)号：US08140834B2
公开(公告)日：2012-03-20
申请号：US12037808
申请日：2008-02-26
CPC分类号： G06F9/4812
摘要： A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.
摘要翻译： 一种用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品。 该方法包括在处理器处接收静止中断请求。 处理器正在以一种模式执行。 识别与该模式相关联的过滤区域。 确定处理器是否可以过滤停顿中断请求。 该确定响应于过滤区域和可编程过滤寄存器的内容，用于指示接收处理器执行的过滤异常。 响应于确定可以对请求进行过滤，过滤掉静默中断请求。
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9.发明授权Method, system, and computer program product for cross-invalidation handling in a multi-level private cache 失效用于多级私有缓存中的交叉无效处理的方法，系统和计算机程序产品公开(公告)号：US07890700B2
公开(公告)日：2011-02-15
申请号：US12051736
申请日：2008-03-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译： 提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。 该系统包括一个处理器。 处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。 该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。 每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。 该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。 响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。
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公开(公告)号：US07039762B2
公开(公告)日：2006-05-02
申请号：US10436217
申请日：2003-05-12
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0851 , G06F12/1063
摘要： A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the parallel processing pipelines wherein each said cache directory is split according to the interleaved cache and interleaving of the cache directory is independent of address bits used for cache interleaving.
摘要翻译： 具有交错缓存和适于访问所有交错高速缓存的两个并行处理流水线的微处理器。 微处理器包括：用于每个并行处理流水线的高速缓存目录，其中每个所述高速缓存目录根据交错的高速缓冲存储器进行分割，并且高速缓存目录的交织与用于高速缓存交错的地址位无关。
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