公开(公告)号：US09054178B2

公开(公告)日：2015-06-09

申请号：US14174822

申请日：2014-02-06

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US08426858B2

公开(公告)日：2013-04-23

申请号：US12956020

申请日：2010-11-30

申请人： Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

发明人： Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

IPC分类号： H01L29/04 ,  H01L31/036

CPC分类号： H01L29/66628 ,  H01L21/26506 ,  H01L29/7834 ,  H01L29/7842

摘要： Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

公开(公告)号：US20110147831A1

公开(公告)日：2011-06-23

申请号：US12646678

申请日：2009-12-23

申请人： Joseph M. Steigerwald ,  Jack Hwang ,  Chi-Hwa Tsang ,  Michael Ollinger ,  Mengcheng Lu

发明人： Joseph M. Steigerwald ,  Jack Hwang ,  Chi-Hwa Tsang ,  Michael Ollinger ,  Mengcheng Lu

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： An exemplary embodiment of a method for forming a gate for a planar-type or a finFET-type transistor comprises forming a gate trench that includes an interior surface. A first work-function metal is formed on the interior surface of the gate trench, and a low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. Another exemplary embodiment provides that a second work-function metal is formed on the first work-function metal, and then the low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof.

摘要翻译： 用于形成平面型或finFET型晶体管的栅极的方法的示例性实施例包括形成包括内表面的栅极沟槽。 第一工作功能金属形成在栅极沟槽的内表面上，并且使用化学气相沉积（CVD）技术或原子层沉积（ALD）沉积在第一功函数金属上的低电阻率材料， 技术或其组合。 另一示例性实施例提供了在第一工作功能金属上形成第二功函数金属，然后使用化学气相沉积（CVD）技术将低电阻率材料沉积在第一功函数金属上，或者使用原子 层沉积（ALD）技术或其组合。

公开(公告)号：US07858981B2

公开(公告)日：2010-12-28

申请号：US12319887

申请日：2009-01-12

申请人： Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

发明人： Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

IPC分类号： H01L29/04 ,  H01L31/036

CPC分类号： H01L29/66628 ,  H01L21/26506 ,  H01L29/7834 ,  H01L29/7842

摘要： Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

摘要翻译： 本发明的一些实施例包括提供碳掺杂区域和升高的源极/漏极区域以在NMOS晶体管沟道中提供拉伸应力。

公开(公告)号：US07479431B2

公开(公告)日：2009-01-20

申请号：US11014937

申请日：2004-12-17

申请人： Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

发明人： Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/26506 ,  H01L29/7834 ,  H01L29/7842

摘要： Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

公开(公告)号：US20060134872A1

公开(公告)日：2006-06-22

申请号：US11014937

申请日：2004-12-17

申请人： Michael Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew Westmeyer

发明人： Michael Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew Westmeyer

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66628 ,  H01L21/26506 ,  H01L29/7834 ,  H01L29/7842

摘要： Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

公开(公告)号：US20110156107A1

公开(公告)日：2011-06-30

申请号：US12655408

申请日：2009-12-30

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US07892971B2

公开(公告)日：2011-02-22

申请号：US12164560

申请日：2008-06-30

申请人： Jack Hwang ,  Sridhar Govindaraju ,  Karson Knutson ,  Harold Kennel ,  Aravind Killampalli

发明人： Jack Hwang ,  Sridhar Govindaraju ,  Karson Knutson ,  Harold Kennel ,  Aravind Killampalli

IPC分类号： H01L21/44

CPC分类号： H01L21/324 ,  H01L21/28518 ,  H01L29/665

摘要： An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.

摘要翻译： 描述用于半导体制造的退火方法和装置。 该方法和装置允许可以跨越热预算的退火，并且可以针对具体过程及其对应的激活能量进行定制。 在一些情况下，退火方法跨越约1毫秒至约1秒的时间范围。 该退火方法的一个实例包括二次退火方法，其中在自杀化处理期间实现镍管形成的减少。 在一些情况下，该方法和装置将亚秒级退火的快速加热速率与导热基板相结合，为硅晶片提供快速冷却。 因此，次秒退火方法的热预算可以跨越从常规RTP退火到闪光退火工艺（包括退火的持续时间，以及峰值温度）的范围。 描述其他实施例。

公开(公告)号：US20060286807A1

公开(公告)日：2006-12-21

申请号：US11156381

申请日：2005-06-16

申请人： Jack Hwang ,  Robert James ,  Eric Lambert ,  Jonathan Leonard ,  Richard Brindos ,  Karson Knutson ,  Mark Armstrong ,  Justin Sandford

发明人： Jack Hwang ,  Robert James ,  Eric Lambert ,  Jonathan Leonard ,  Richard Brindos ,  Karson Knutson ,  Mark Armstrong ,  Justin Sandford

IPC分类号： H01L21/306 ,  G01R31/00 ,  H01L21/461

CPC分类号： H01L21/67115 ,  H01L21/67248

摘要： Embodiments relate to a substrate or wafer edge support having an emmisivity greater than that of a silicon wafer, where the edge support is for supporting a wafer during processing to form circuit devices on or in the wafer. Embodiments also include temperature sensors, heat conducting gas jets, and photonic energy can be directed to sense and control the temperature of the edge support and/or wafer edge during annealing to reduce temperature roll-off or roll-up at the edge as compared to the center of the wafer. Specifically, use of an edge support having an emmisivity greater than or equal to that of the wafer during processing allows helium gas jets directed at the edge support and/or wafer edge to reduce temperature roll-up at the edge during annealing. Because wafers from different processes and anneal locations may all have different emmisivities, use of the feedback loop will enable one edge ring to support the uniform anneal of wafers with a range of different emmisivities.

公开(公告)号：US20050211697A1

公开(公告)日：2005-09-29

申请号：US10815068

申请日：2004-03-26

申请人： Karson Knutson ,  Jack Hwang

发明人： Karson Knutson ,  Jack Hwang

IPC分类号： F27B5/14 ,  F27B17/00 ,  F27D11/00 ,  H01L21/00

CPC分类号： H01L21/67115 ,  F27B17/0025

摘要： A method, apparatus, and system including a reflecting device having a plurality of reflecting zones with associated reflectivities for reflecting light from a flash lamp, are described herein.

摘要翻译： 本文描述了一种包括具有多个反射区域的反射装置的方法，装置和系统，其具有用于反射来自闪光灯的光的相关联的反射率。