-
公开(公告)号：US20050221610A1
公开(公告)日：2005-10-06
申请号：US11144980
申请日：2005-06-03
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis Warner , Erdem Kaltalioglu
IPC分类号： H01L23/522 , H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。
-
公开(公告)号：US07368804B2
公开(公告)日：2008-05-06
申请号：US10439874
申请日：2003-05-16
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。
-
公开(公告)号：US07786007B2
公开(公告)日：2010-08-31
申请号：US12098976
申请日：2008-04-07
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。
-
公开(公告)号：US20080213993A1
公开(公告)日：2008-09-04
申请号：US12098976
申请日：2008-04-07
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。
-
公开(公告)号：US07052621B2
公开(公告)日：2006-05-30
申请号：US10461090
申请日：2003-06-13
申请人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
发明人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
IPC分类号： C23F1/00
CPC分类号： H01L21/76832 , H01L21/0332 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1036 , Y10T428/12576 , Y10T428/12806 , Y10T428/265 , Y10T428/31678
摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).
摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。
-
公开(公告)号：US07241681B2
公开(公告)日：2007-07-10
申请号：US11330834
申请日：2006-01-12
申请人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
发明人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/0332 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1036 , Y10T428/12576 , Y10T428/12806 , Y10T428/265 , Y10T428/31678
摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).
摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。
-
7.发明授权Reduction of the shear stress in copper via's in organic interlayer dielectric material 有权在有机层间介质材料中减少铜通道中的剪切应力公开(公告)号：US07060619B2
公开(公告)日：2006-06-13
申请号：US10379346
申请日：2003-03-04
申请人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
发明人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.
摘要翻译： 形成包含逻辑电路（微处理器，Asics或其他）或随机存取存储器单元（DRAMS）的半导体主体上的互连层以显着减少相邻导体/通孔之间的短路数量的方式形成， 0.18微米或更小。 这是通过蚀刻完成的，以在化学机械抛光工艺完成后在每一层上形成凹陷的铜顶表面。 在凹陷的铜表面上施加的阻挡层的厚度被控制成与周围的绝缘体表面基本上共面。 较厚的阻挡层消除了对覆盖层的需要。 消除覆盖层导致整体电容耦合，应力和成本的降低。
-
公开(公告)号：US20050077628A1
公开(公告)日：2005-04-14
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.
-
公开(公告)号：US07091612B2
公开(公告)日：2006-08-15
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas C. La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas C. La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.
-
公开(公告)号：US20060113278A1
公开(公告)日：2006-06-01
申请号：US11330834
申请日：2006-01-12
申请人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew Simon , Mark Hoinkis , Steffen Kaldor , Chih-Chao Yang
发明人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew Simon , Mark Hoinkis , Steffen Kaldor , Chih-Chao Yang
CPC分类号： H01L21/76832 , H01L21/0332 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1036 , Y10T428/12576 , Y10T428/12806 , Y10T428/265 , Y10T428/31678
摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).
摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。
-
-
-
-
-
-
-
-
-
搜索结果
77 条记录 (耗时 0.025 秒)
