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    Semiconductor devices with pocket implant and counter doping
    2.
    发明授权
    Semiconductor devices with pocket implant and counter doping 有权
    具有袋式注入和反掺杂的半导体器件

    公开(公告)号：US06228725B1

    公开(公告)日：2001-05-08

    申请号：US09281543

    申请日：1999-03-30

    申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

    发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

    IPC分类号： H01L21336

    CPC分类号： H01L29/66575 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7838

    摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).

    摘要翻译： 形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。 晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。 通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。 第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

    Transistor having ultrashallow source and drain junctions with reduced gate overlap and method
    4.
    发明授权
    Transistor having ultrashallow source and drain junctions with reduced gate overlap and method 有权
    具有超低源极和漏极结的晶体管具有减少的栅极重叠和方法

    公开(公告)号：US5976937A

    公开(公告)日：1999-11-02

    申请号：US136750

    申请日：1998-08-19

    申请人： Mark S. Rodder ,  Mahalingam Nandakumar

    发明人： Mark S. Rodder ,  Mahalingam Nandakumar

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/1083 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/66492 ,  H01L29/6659

    摘要： Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) may be formed substantially perpendicular to the first gate electrode (124) and separated from a second active area (142) of the semiconductor layer by a second gate insulator (146). A masking layer (160) may be formed over the semiconductor layer (112) and expose a source and a drain section (162 and 164) of the first active area (126) and a source and a drain section (166 and 168) of the second active area (142). Dopants may be implanted from a first direction substantially parallel to the first gate electrode (124) into the source and drain sections (166 and 168) of the first active area (126). The dopants are implanted in the first direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (166 and 168) of the second active area (142). Dopants may be implanted from a second direction substantially parallel to the second gate electrode (140) and perpendicular to the first direction into the source and drain sections (166 and 168) of the second active area (142). The dopants are implanted in the second direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (162 and 164) of the first active area (126).

    摘要翻译： 制造具有减少的栅极重叠的超短源极和漏极结的晶体管的方法可以包括通过第一栅极绝缘体（130）形成与半导体层（112）的第一有源区（126）分离的第一栅电极（124）。 第二栅极电极（140）可以形成为基本上垂直于第一栅电极（124）并且通过第二栅极绝缘体（146）与半导体层的第二有源区域（142）分离。 可以在半导体层（112）之上形成掩模层（160）并且暴露第一有源区域（126）的源极和漏极部分（162和164）以及源极和漏极部分（166和168） 第二活动区域（142）。 掺杂剂可以从基本上平行于第一栅电极（124）的第一方向注入到第一有源区（126）的源区和漏区（166和168）中。 所述掺杂剂以所述掩蔽层（160）阻止所述掺杂剂进入所述第二有源区域（142）的源极和漏极部分（166和168）的角度沿所述第一方向植入。 掺杂剂可以从基本上平行于第二栅电极（140）并垂直于第一方向的第二方向注入第二有源区（142）的源区和漏区（166和168）中。 所述掺杂剂以所述掩蔽层（160）阻挡所述掺杂剂进入所述第一有源区（126）的源区和漏区（162和164）的角度在第二方向上注入。

    Semiconductor devices with pocket implant and counter doping
    5.
    发明授权
    Semiconductor devices with pocket implant and counter doping 失效
    具有袋式注入和反掺杂的半导体器件

    公开(公告)号：US5917219A

    公开(公告)日：1999-06-29

    申请号：US725599

    申请日：1996-10-03

    申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

    发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0397

    CPC分类号： H01L29/66575 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7838

    摘要： A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').

    摘要翻译： 形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。 晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。 通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。 第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

    Controlled oxide growth over polysilicon gates for improved transistor characteristics
    7.
    发明授权
    Controlled oxide growth over polysilicon gates for improved transistor characteristics 有权
    在多晶硅栅极上控制氧化物生长，以改善晶体管特性

    公开(公告)号：US06352900B1

    公开(公告)日：2002-03-05

    申请号：US09618404

    申请日：2000-07-18

    申请人： Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

    发明人： Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L21/28247

    摘要： A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).

    摘要翻译： 一种在晶体管栅极上控制氧化物生长的方法。 第一膜（40）形成在半导体衬底（10）上。 该膜植入第一种并图案化以形成晶体管栅极（45）。 晶体管栅极（45）和半导体衬底（10）被注入第二种类，并且晶体管栅极（45）被氧化以在晶体管栅极（45）的侧表面上产生氧化物膜（80）。

    Versatile system for forming uniform wafer surfaces
    8.
    发明授权
    Versatile system for forming uniform wafer surfaces 有权
    用于形成均匀晶片表面的通用系统

    公开(公告)号：US06635584B2

    公开(公告)日：2003-10-21

    申请号：US10229480

    申请日：2002-08-28

    申请人： Zhiqiang Jeff Wu ,  Mark S. Rodder ,  Manoj Mehrotra

    发明人： Zhiqiang Jeff Wu ,  Mark S. Rodder ,  Manoj Mehrotra

    IPC分类号： H01L2131

    CPC分类号： H01L21/28247 ,  H01L21/28123

    摘要： A system for fabricating an integrated circuit is disclosed that includes providing a semiconductor substrate (10), and forming a gate oxide layer (12) on an active area on the substrate. A polysilicon gate (14) is formed, on top of the gate oxide, by etching. Etch damage (16) on the substrate surface is repaired by anneal in an inert gas environment—e.g., He, Ne, N2, Ar gas, or combinations thereof.

    摘要翻译： 公开了一种用于制造集成电路的系统，其包括提供半导体衬底（10），以及在衬底上的有源区上形成栅极氧化物层（12）。 通过蚀刻在栅极氧化物的顶部上形成多晶硅栅极（14）。 在惰性气体环境（例如He，Ne，N 2，Ar气体或其组合）中通过退火来修复基底表面上的蚀刻损伤（16）。

    Sub-critical-dimension integrated circuit features
    9.
    发明授权
    Sub-critical-dimension integrated circuit features 有权

    公开(公告)号：US06686300B2

    公开(公告)日：2004-02-03

    申请号：US10055262

    申请日：2001-10-25

    申请人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

    发明人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

    IPC分类号： H01L21302

    CPC分类号： H01L29/4238 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/1033 ,  Y10S438/945

    摘要： A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.