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86 条记录 (耗时 0.025 秒)

    Sub-critical-dimension integrated circuit features
    1.
    发明授权
    Sub-critical-dimension integrated circuit features 有权

    公开(公告)号：US06686300B2

    公开(公告)日：2004-02-03

    申请号：US10055262

    申请日：2001-10-25

    申请人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

    发明人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

    IPC分类号： H01L21302

    CPC分类号： H01L29/4238 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/1033 ,  Y10S438/945

    摘要： A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

    Controlled oxide growth over polysilicon gates for improved transistor characteristics
    2.
    发明授权
    Controlled oxide growth over polysilicon gates for improved transistor characteristics 有权
    在多晶硅栅极上控制氧化物生长，以改善晶体管特性

    公开(公告)号：US06352900B1

    公开(公告)日：2002-03-05

    申请号：US09618404

    申请日：2000-07-18

    申请人： Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

    发明人： Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L21/28247

    摘要： A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).

    摘要翻译： 一种在晶体管栅极上控制氧化物生长的方法。 第一膜（40）形成在半导体衬底（10）上。 该膜植入第一种并图案化以形成晶体管栅极（45）。 晶体管栅极（45）和半导体衬底（10）被注入第二种类，并且晶体管栅极（45）被氧化以在晶体管栅极（45）的侧表面上产生氧化物膜（80）。

    Versatile system for forming uniform wafer surfaces
    3.
    发明授权
    Versatile system for forming uniform wafer surfaces 有权
    用于形成均匀晶片表面的通用系统

    公开(公告)号：US06635584B2

    公开(公告)日：2003-10-21

    申请号：US10229480

    申请日：2002-08-28

    申请人： Zhiqiang Jeff Wu ,  Mark S. Rodder ,  Manoj Mehrotra

    发明人： Zhiqiang Jeff Wu ,  Mark S. Rodder ,  Manoj Mehrotra

    IPC分类号： H01L2131

    CPC分类号： H01L21/28247 ,  H01L21/28123

    摘要： A system for fabricating an integrated circuit is disclosed that includes providing a semiconductor substrate (10), and forming a gate oxide layer (12) on an active area on the substrate. A polysilicon gate (14) is formed, on top of the gate oxide, by etching. Etch damage (16) on the substrate surface is repaired by anneal in an inert gas environment—e.g., He, Ne, N2, Ar gas, or combinations thereof.

    摘要翻译： 公开了一种用于制造集成电路的系统，其包括提供半导体衬底（10），以及在衬底上的有源区上形成栅极氧化物层（12）。 通过蚀刻在栅极氧化物的顶部上形成多晶硅栅极（14）。 在惰性气体环境（例如He，Ne，N 2，Ar气体或其组合）中通过退火来修复基底表面上的蚀刻损伤（16）。

    INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME
    6.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME 有权
    包括FINFET的集成电路器件及其形成方法

    公开(公告)号：US20150243756A1

    公开(公告)日：2015-08-27

    申请号：US14698402

    申请日：2015-04-28

    申请人： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

    发明人： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66522 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    摘要： Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.

    摘要翻译： 提供了形成finFET的方法。 所述方法可以包括在衬底上形成包括铟（In）的鳍状沟道区域，形成与衬底上的沟道区相邻的深源极/漏极区域，并在沟道区域和深度之间形成源极/漏极延伸区域 源/漏区。 源极/漏极延伸区域的相对侧壁可以分别接触沟道区域和深源极/漏极区域，并且源极/漏极延伸区域可以包括In y Ga 1-y As，y在约0.3至约0.5的范围内。

    Trench isolation structure and a method of manufacture therefor
    9.
    发明授权
    Trench isolation structure and a method of manufacture therefor 有权
    沟槽隔离结构及其制造方法

    公开(公告)号：US07371658B2

    公开(公告)日：2008-05-13

    申请号：US10870020

    申请日：2004-06-17

    申请人： Rick L. Wise ,  Mark S. Rodder

    发明人： Rick L. Wise ,  Mark S. Rodder

    IPC分类号： H01L21/76 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76224 ,  H01L21/823807 ,  H01L21/823878

    摘要： The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

    摘要翻译： 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁上的缓冲层（133）。 沟槽隔离结构（130）还包括位于缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

    Semiconductor devices with pocket implant and counter doping
    10.
    发明授权
    Semiconductor devices with pocket implant and counter doping 有权
    具有袋式注入和反掺杂的半导体器件

    公开(公告)号：US06228725B1

    公开(公告)日：2001-05-08

    申请号：US09281543

    申请日：1999-03-30

    申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

    发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

    IPC分类号： H01L21336

    CPC分类号： H01L29/66575 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7838

    摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).

    摘要翻译： 形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。 晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。 通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。 第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。