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    System serialization with early release of individual processor
    3.
    发明授权
    System serialization with early release of individual processor 失效
    系统串行化与早期发布的单个处理器

    公开(公告)号：US6119219A

    公开(公告)日：2000-09-12

    申请号：US70595

    申请日：1998-04-30

    申请人： Charles Franklin Webb ,  Dean G. Bair ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Pak-kin Mak ,  Jennifer Almoradie Navarro ,  Timothy John Slegel

    发明人： Charles Franklin Webb ,  Dean G. Bair ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Pak-kin Mak ,  Jennifer Almoradie Navarro ,  Timothy John Slegel

    IPC分类号： G06F15/177 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/52 ,  G06F9/00

    CPC分类号： G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/3834

    摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.

    摘要翻译： 一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括 多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作 操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。 此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

    System for use in translating virtual addresses into absolute addresses
    4.
    发明授权
    System for use in translating virtual addresses into absolute addresses 失效
    用于将虚拟地址转换为绝对地址的系统

    公开(公告)号：US5649140A

    公开(公告)日：1997-07-15

    申请号：US414671

    申请日：1995-03-31

    申请人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

    发明人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

    IPC分类号： G06F12/10 ,  G06F9/26 ,  G06F9/34 ,  G06F12/00 ,  G06F12/02

    CPC分类号： G06F12/109 ,  G06F12/10

    摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

    摘要翻译： 在处理系统中，在虚拟地址和绝对地址之间便于翻译。 该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。 加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。 逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。 该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。 从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

    Multiprocessor serialization with early release of processors
    5.
    发明授权
    Multiprocessor serialization with early release of processors 失效
    多处理器串行化与早期版本的处理器

    公开(公告)号：US06079013A

    公开(公告)日：2000-06-20

    申请号：US70429

    申请日：1998-04-30

    申请人： Charles Franklin Webb ,  Dean G. Bair ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Pak-kin Mak ,  Jennifer Almoradie Navarro ,  Timothy John Slegel

    发明人： Charles Franklin Webb ,  Dean G. Bair ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Pak-kin Mak ,  Jennifer Almoradie Navarro ,  Timothy John Slegel

    IPC分类号： G06F9/52 ,  G06F9/318 ,  G06F12/06

    CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3017

    摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.

    摘要翻译： 一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括 多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作 操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。 此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

    System speed loading of a writable cache code array
    6.
    发明授权
    System speed loading of a writable cache code array 失效
    可写缓存代码数组的系统速度加载

    公开(公告)号：US6105109A

    公开(公告)日：2000-08-15

    申请号：US26327

    申请日：1998-02-19

    申请人： Barry Watson Krumm ,  Charles Franklin Webb ,  Timothy John Slegel ,  Mark Steven Farrell ,  Yuen Hung Chan

    发明人： Barry Watson Krumm ,  Charles Franklin Webb ,  Timothy John Slegel ,  Mark Steven Farrell ,  Yuen Hung Chan

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/00 ,  G06F9/28

    CPC分类号： G06F9/3802 ,  G06F12/0802

    摘要： SMP computers systems can add to the first level cache a fill mode latch and achieve straightforward, high-performance loading of a writable cache code array that is part of a hierarchical cache structure.A new code array's write control elements include a control latch called "fill mode" for the BCE controls which when fill mode is active, then a disable is also active, since reads of the code array may not give accurate data when the array is not yet filled-up/fully valid. New mode follows the sequential steps which process code by:a) purge the cache array; thenb) disable the code array; thenc) turn on fill mode with a buffer control element fill mode latch; and then processd) code increments once through a range of line addresses, where the range is at least as wide as the range(s) specified in the code array's lookup mechanism.e) turn off fill mode; thenf) purge the cache array again: and theng) enable the code array (turn off the code array disable bit).h) resume normal operation to end the sequence.

    摘要翻译： SMP计算机系统可以将第一级缓存添加到填充模式锁存器中，并实现作为分层缓存结构的一部分的可写缓存代码数组的直接，高性能加载。新的代码数组的写控制元素包括称为“ 填充模式“，当填充模式处于活动状态时，禁用也是活动的，因为当数组尚未填满/完全有效时，代码数组的读取可能无法提供准确的数据。 新模式遵循以下步骤处理代码的顺序步骤：a）清除缓存数组; 那么b）禁用代码数组; 然后c）用缓冲器控制元件填充模式锁存器打开填充模式; 然后处理d）通过行地址范围增加一次代码，其范围至少与代码数组查找机制中指定的范围一样宽。 e）关闭填充模式; 然后f）再次清除缓存数组：然后g）启用代码数组（关闭代码数组禁用位）。 h）恢复正常操作以结束序列。

    Method for use in translating virtual addresses into absolute addresses
    8.
    发明授权
    Method for use in translating virtual addresses into absolute addresses 失效
    用于将虚拟地址转换为绝对地址的方法

    公开(公告)号：US5684975A

    公开(公告)日：1997-11-04

    申请号：US453140

    申请日：1995-05-30

    申请人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

    发明人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

    IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F12/02

    CPC分类号： G06F12/109 ,  G06F12/10

    摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

    摘要翻译： 在处理系统中，在虚拟地址和绝对地址之间便于翻译。 该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。 加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。 逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。 该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。 从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

    Computer with optimizing hardware for conditional hedge fetching into cache storage
    9.
    发明授权
    Computer with optimizing hardware for conditional hedge fetching into cache storage 失效
    具有优化硬件的计算机，用于将条件对冲提取到高速缓存存储中

    公开(公告)号：US6035392A

    公开(公告)日：2000-03-07

    申请号：US26923

    申请日：1998-02-20

    申请人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

    发明人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

    IPC分类号： G06F9/38 ,  G06F9/00

    CPC分类号： G06F9/3804

    摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to he fetched.

    摘要翻译： 一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中 结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择 对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的 当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求 高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复该提取请求，该数据不在高速缓存中以在稍后重复该提取请求 更确定正在执行的进程想要数据的时间，或者在确定正在执行的进程不需要他获取的数据的情况下，永远不会重复该请求。

    Method for conditional hedge fetching into cache storage
    10.
    发明授权
    Method for conditional hedge fetching into cache storage 失效
    用于条件对冲取入缓存存储的方法

    公开(公告)号：US6026488A

    公开(公告)日：2000-02-15

    申请号：US27153

    申请日：1998-02-20

    申请人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

    发明人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804

    摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to be fetched.

    摘要翻译： 一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中 结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择 对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的 当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求 高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复获取请求，否则数据不在高速缓存中，以在一个 稍后时间，当确定正在执行的进程想要数据时，或者在确定正在执行的进程不需要要获取的数据的情况下从不重复该请求。