公开(公告)号：US06624032B2

公开(公告)日：2003-09-23

申请号：US10102319

申请日：2002-03-20

申请人： Mohsen Alavi ,  Ebrahim Andideh ,  Scott Thompson ,  Mark T. Bohr

发明人： Mohsen Alavi ,  Ebrahim Andideh ,  Scott Thompson ,  Mark T. Bohr

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7841

摘要： A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

公开(公告)号：US06392271B1

公开(公告)日：2002-05-21

申请号：US09342022

申请日：1999-06-28

申请人： Mohsen Alavi ,  Ebrahim Andideh ,  Scott Thompson ,  Mark T. Bohr

发明人： Mohsen Alavi ,  Ebrahim Andideh ,  Scott Thompson ,  Mark T. Bohr

IPC分类号： H01L2976

CPC分类号： H01L29/66666 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7841

摘要： A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer sited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

摘要翻译： 一种双栅极晶体管器件及其制造方法。 首先，在掺杂衬底上的图案化氧化物层上制备掺杂衬底，其限定沟道。 接下来，沉积硅层以形成沟道，然后栅极氧化层在沟道附近生长。 随后，在栅氧化层旁边形成多个栅电极，在沟道上形成漏极。 在形成漏极之后，设置ILD层。 该ILD层被蚀刻以形成源极区接触，漏极区接触，第一栅电极接触和第二栅电极接触。

公开(公告)号：US06258700B1

公开(公告)日：2001-07-10

申请号：US09313830

申请日：1999-05-18

申请人： Mark T. Bohr ,  Mohsen Alavi

发明人： Mark T. Bohr ,  Mohsen Alavi

IPC分类号： H01L21326

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the suicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.

摘要翻译： 一种设置在半导体衬底上用于提供任意电连接的可熔连接装置。 本发明的可熔连接装置包括硅化物层和形成在硅化物层上并具有第一非编程电阻的多晶硅层。 硅化物层聚集形成响应于在硅化物层上施加的预定编程电位的电中断，使得可熔接线器件的电阻可以选择性地增加到第二编程电阻。

公开(公告)号：US5969404A

公开(公告)日：1999-10-19

申请号：US895325

申请日：1997-07-16

申请人： Mark T. Bohr ,  Mohsen Alavi

发明人： Mark T. Bohr ,  Mohsen Alavi

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first unprogrammed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance

摘要翻译： 一种设置在半导体衬底上用于提供任意电连接的可熔连接装置。 本发明的熔断连接装置包括在硅化物层上形成的硅化物层和多晶硅层，并具有第一未编程电阻。 硅化物层聚集形成响应于跨越硅化物层施加的预定编程电位的电中断，使得可熔接头装置的电阻可以选择性地增加到第二编程电阻

公开(公告)号：US5708291A

公开(公告)日：1998-01-13

申请号：US537283

申请日：1995-09-29

申请人： Mark T. Bohr ,  Mohsen Alavi

发明人： Mark T. Bohr ,  Mohsen Alavi

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.

摘要翻译： 一种设置在半导体衬底上用于提供任意电连接的可熔连接装置。 本发明的可熔连接装置包括硅化物层和形成在硅化物层上并具有第一非编程电阻的多晶硅层。 硅化物层聚集形成响应于跨过硅化物层施加的预定编程电位的电中断，使得熔丝连接装置的电阻可以选择性地增加到第二编程电阻。

公开(公告)号：US06337507B1

公开(公告)日：2002-01-08

申请号：US08769152

申请日：1996-12-18

申请人： Mark T. Bohr ,  Mohsen Alavi ,  Min-Chun Tsai

发明人： Mark T. Bohr ,  Mohsen Alavi ,  Min-Chun Tsai

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fusible link device disposed on a semiconductor substrate for providing discretionary changes in resistance. The fusible link device of the invention includes a polysilicon layer having a first resistance. A silicide layer formed on the polysilicon layer has a second, lower resistance and includes a fuse region having a first notched region narrower than the center of the fuse region, a first contact region electrically coupled to one end of the fuse region and a second contact region electrically coupled to an opposite end of the fuse region. The silicide layer agglomerates to form an electrical discontinuity in the fuse region (usually in the notched region) in response to a current greater than or equal to a predetermined programming current flowing between the contact regions, such that the resistance of the fusible link device can be selectively increased.

摘要翻译： 一种设置在半导体衬底上的可熔连接装置，用于提供任意改变的电阻。 本发明的熔断连接装置包括具有第一电阻的多晶硅层。 形成在多晶硅层上的硅化物层具有第二较低电阻，并且包括具有比熔丝区域的中心窄的第一缺口区域的熔丝区域，电耦合到熔丝区域的一端的第一接触区域和第二接触点 区域电耦合到保险丝区域的相对端。 硅化物层响应于大于或等于在接触区域之间流动的预定编程电流的电流而聚集在熔丝区域（通常在缺口区域中）形成电中断，使得可熔连接装置的电阻可以 有选择地增加。

公开(公告)号：US20060139995A1

公开(公告)日：2006-06-29

申请号：US11027476

申请日：2004-12-28

申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC分类号： G11C11/34

CPC分类号： G11C17/146 ,  G11C17/12

摘要： A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.

摘要翻译： 一次性可编程存储器包括隔离栅极晶体管，其可以通过使隔离栅极晶体管受到降低隔离栅极晶体管特性的电压条件而被编程。 可以感测劣化的特性以读取存储器。

公开(公告)号：US20050285616A1

公开(公告)日：2005-12-29

申请号：US10880337

申请日：2004-06-29

申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC分类号： G01R19/165 ,  G01R31/26

CPC分类号： G01R31/2621 ,  G01R19/16571

摘要： A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.

摘要翻译： 由于过电压状态，晶体管可能具有劣化特性。 可以感测劣化特性以确定晶体管先前已经经受过压状态。

公开(公告)号：US07102358B2

公开(公告)日：2006-09-05

申请号：US10880337

申请日：2004-06-29

申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H Tang ,  Mohsen Alavi ,  Vivek K De

发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H Tang ,  Mohsen Alavi ,  Vivek K De

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R19/16571

摘要： A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.

摘要翻译： 由于过电压状态，晶体管可能具有劣化特性。 可以感测劣化特性以确定晶体管先前已经经受过压状态。

公开(公告)号：US5844300A

公开(公告)日：1998-12-01

申请号：US716843

申请日：1996-09-19

申请人： Mohsen Alavi ,  Payman Aminzadeh ,  Robert A. Gasser ,  Sunit Tyagi ,  Gilroy J. Vandentop

发明人： Mohsen Alavi ,  Payman Aminzadeh ,  Robert A. Gasser ,  Sunit Tyagi ,  Gilroy J. Vandentop

IPC分类号： H01L27/115 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L27/115

摘要： A monitoring device to monitor process induced charge employing a single layer of polysilicon forming a floating gate. The device comprises two capacitors, one for charging and the other for discharging a floating gate of an n-channel transistor. Embodiments which permit the monitoring of positive charge, negative charge and both positive and negative charge are described. The device is reusable and lends itself to in-line monitoring as opposed to some prior art devices used for end-of-line monitoring.

摘要翻译： 一种使用形成浮栅的单层多晶硅监测过程感应电荷的监测装置。 该器件包括两个电容器，一个用于充电，另一个用于放电n沟道晶体管的浮置栅极。 描述允许监测正电荷，负电荷以及正电荷和负电荷两者的实施例。 与用于线路末端监测的一些现有技术设备相反，该设备可重复使用并且适合于在线监测。