利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

116 条记录 (耗时 0.024 秒)

    Method for forming bit lines for semiconductor devices
    2.
    发明授权
    Method for forming bit lines for semiconductor devices 有权
    用于形成半导体器件的位线的方法

    公开(公告)号：US07811915B2

    公开(公告)日：2010-10-12

    申请号：US12048549

    申请日：2008-03-14

    申请人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

    发明人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

    IPC分类号： H01L21/22

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.

    摘要翻译： 一种形成半导体器件的方法包括在衬底的第一部分上形成第一介电层，在第一介电层上形成电荷存储层，并蚀刻电荷存储层和第一介电层中的沟槽，其中沟槽延伸 到基底。 该方法还包括将n型杂质注入到衬底中以形成具有第一深度和第一宽度的n型区域，并且在植入n型杂质之后将p型杂质注入到衬底中，形成p型杂质 具有第二深度和第二宽度的p型区域。 该方法还包括在电荷存储层上形成第二电介质层，并在第二电介质层上形成控制栅极。

    Method for forming bit lines for semiconductor devices
    4.
    发明授权
    Method for forming bit lines for semiconductor devices 有权
    用于形成半导体器件的位线的方法

    公开(公告)号：US07972948B2

    公开(公告)日：2011-07-05

    申请号：US12880541

    申请日：2010-09-13

    申请人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

    发明人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

    IPC分类号： H01L21/22

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.

    摘要翻译： 存储器件包括多个存储器单元和多个位线。 每个位线包括具有第一宽度和第一深度的第一区域和具有第二宽度和第二深度的第二区域，其中第一宽度小于第二宽度。 第一区域可以包括n型杂质，第二区域可以包括p型杂质。

    METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES
    5.
    发明申请
    METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES 有权
    用于形成半导体器件的位线的方法

    公开(公告)号：US20100330762A1

    公开(公告)日：2010-12-30

    申请号：US12880541

    申请日：2010-09-13

    申请人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

    发明人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,

    摘要翻译： 存储器件包括多个存储器单元和多个位线。 每个位线包括具有第一宽度和第一深度的第一区域和具有第二宽度和第二深度的第二区域，其中第一宽度小于第二宽度。 第一区域可以包括n型杂质，第二区域可以包括p型杂质，

    Bit line implant
    6.
    发明授权
    Bit line implant 有权
    位线植入

    公开(公告)号：US07432178B2

    公开(公告)日：2008-10-07

    申请号：US11254769

    申请日：2005-10-21

    申请人： Angela T. Hui ,  Jean Yang ,  Yu Sun ,  Mark T. Ramsbey ,  Weidong Qian

    发明人： Angela T. Hui ,  Jean Yang ,  Yu Sun ,  Mark T. Ramsbey ,  Weidong Qian

    IPC分类号： H01L21/04

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.

    摘要翻译： 公开了一种用于执行位线植入的方法。 该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。 该组结构的每个结构包括多晶硅部分和硬掩模部分。 该组结构的第一结构与该组结构的第二结构分开小于100纳米。 该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

    Hard mask spacer for sublithographic bitline
    7.
    发明授权
    Hard mask spacer for sublithographic bitline 有权
    用于亚光刻位线的硬掩模垫片

    公开(公告)号：US06962849B1

    公开(公告)日：2005-11-08

    申请号：US10729732

    申请日：2003-12-05

    申请人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh ,  Mark T. Ramsbey ,  Ashok M. Khathuria

    发明人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh ,  Mark T. Ramsbey ,  Ashok M. Khathuria

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

    摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 在形成过程中使用间隔物来减小存储器中的掩埋位线的尺寸，这适用于存储用于计算机等的数据。 较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。 位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。 以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。 此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。

    Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming
    9.
    发明授权
    Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming 有权
    双用途抗反射涂层和闪存间隔器等双栅技术及成型方法

    公开(公告)号：US06798002B1

    公开(公告)日：2004-09-28

    申请号：US09607675

    申请日：2000-06-30

    申请人： Robert B. Ogle, Jr. ,  Tuan D. Pham ,  Mark T. Ramsbey

    发明人： Robert B. Ogle, Jr. ,  Tuan D. Pham ,  Mark T. Ramsbey

    IPC分类号： H01L27108

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

    摘要： A dual gate semiconductor device, such as a flash memory semiconductor device, whose plurality of dual gate sidewall spacer structure is formed by a first and second anti-reflection fabrication process. The sidewall spacers of the dual transistor gate structures in the core memory region are left coated with the second anti-reflective coating material, after being used for gate patterning, to act as sidewall spacers for use in subsequent ion implant and salicidation fabrication steps. The second anti-reflective coating material is selected from a material group such as silicon oxynitride (SiON), silicon nitride (Si3N4), and silicon germanium (SiGe), or other anti-reflective coating material having optical properties and that are compatible with the subsequent implant and salicidation steps.

    摘要翻译： 诸如闪存半导体器件的双栅极半导体器件，其多个双栅极侧壁间隔结构通过第一和第二抗反射制造工艺形成。 核心存储器区域中的双晶体管栅极结构的侧壁间隔物在用于栅极图案化之后被第二抗反射涂层材料涂覆以用作用于后续离子注入和盐化制造步骤的侧壁间隔物。 第二抗反射涂层材料选自诸如氮氧化硅（SiON），氮化硅（Si 3 N 4）和硅锗（SiGe）的材料组或具有光学性质的其它抗反射涂层材料，并且与 随后的植入和盐化步骤。

    Salicided gate for virtual ground arrays
    10.
    发明授权
    Salicided gate for virtual ground arrays 有权
    用于虚拟地面阵列的闸门

    公开(公告)号：US06730564B1

    公开(公告)日：2004-05-04

    申请号：US10217821

    申请日：2002-08-12

    申请人： Mark T. Ramsbey ,  Yu Sun ,  Chi Chang ,  Hidehiko Shiraiwa

    发明人： Mark T. Ramsbey ,  Yu Sun ,  Chi Chang ,  Hidehiko Shiraiwa

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  Y10S438/954

    摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.

    摘要翻译： 本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。 根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。 未图案化的层保护字线之间的基板不会变成水银。 本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。 这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。